veilog

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Here are 3 public repositories matching this topic...

sagniknitr / Reconfigurable-Lab-Project

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8 bit MCU design in Zedboard

fpga vhdl embedded-systems zedboard reconfigurable-computing veilog

Updated Apr 8, 2017
VHDL

aryaempi / verilog-arbitrary-function-generator

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A Verilog HDL implementation of an 8-bit Arbitrary Function Generator with seven selectable waveforms, adjustable frequency and amplitude, and PWM DAC output.

modelsim veilog

Updated Sep 7, 2026
Verilog

ubyhzargam / OpenSTA

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Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed

electronics hdl vlsi sta opensta veilog

Updated Dec 4, 2024
Verilog

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