A simple sram controller and test for the altera DE1 FPGA board
-
Updated
Apr 2, 2019 - VHDL
#
terasic-de1
Here are 4 public repositories matching this topic...
This project smooths a noisy triangular signal using a four-sample moving average implemented in VHDL on a Terasic DE2-115. It reads signed 8-bit samples from ROM, writes the results to RAM, and shows the original and filtered values side by side on the board's seven-segment displays.
-
Updated
Oct 8, 2026 - VHDL
8-bit multicycle processor in VHDL (extends a university design): exhaustive GHDL ALU/sub-unit verification, 8-testbench regression, DE1 port preparation.
fpga processor vhdl embedded-systems computer-architecture ghdl digital-design cpu-design terasic-de1 cyclone-ii
-
Updated
Oct 9, 2026 - VHDL
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
vhdl altera seven-segment vhdl-modules seven-segments-display altera-fpga vhdl-coursework seven-segment-display altera-de1 terasic-de1
-
Updated
Apr 12, 2019 - VHDL
Add this topic to your repo
To associate your repository with the terasic-de1 topic, visit your repo's landing page and select "manage topics."