cyclone-ii

ASK2CB Cyclone II FPGA dev board documentation and examples

VHDL hardware accelerators for Cyclone II FPGA with MCU apps in C for Nios II CPU

Como projeto final da disciplina de Sistemas Digitais (COMP0514), me propus a desenvolver um Processador de Ciclo Único Específico para um Robô Seguidor de Linha.

Flappy Bird on FPGA using VHDL

Implementação de um cronômetro digital com memória em Verilog, para a placa de desenvolvimento FPGA Altera Cyclone II. Projeto acadêmico.

Educational 8-bit VHDL CPU-style datapath for Cyclone II with FSM control, one-hot opcode decoding, ALUs, seven-segment output, waveforms, and parity checking.

8-bit multicycle processor in VHDL (extends a university design): exhaustive GHDL ALU/sub-unit verification, 8-testbench regression, DE1 port preparation.

A Wordle-inspired 4-digit number guessing game implemented in Verilog HDL on an Altera DE2 FPGA with VGA output

Real-time multi-layer guitar looper pedal on Altera DE1 (Cyclone II) — VHDL, 8 MB SDRAM, WM8731 codec. Hobby project, 2008-2009.

Synthesizable 16-bit integer square-root core in VHDL, exhaustively simulated over all 65,536 inputs, with a Terasic DE1 wrapper.

12-bit educational microprocessor implemented and verified in VHDL and Intel/Altera Quartus.

Kitchen-timer on Altera DE1 FPGA development kit - VHDL

422001423701 - Thực hành thiết kế SoC