logicsynthesis

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LAKSHMAN1410 / PUF-for-Secure-Hardware-Authentication-FPGA-ASIC-Implementation-

Design and implementation of a hybrid XOR-based Arbiter Physical Unclonable Function (PUF) on FPGA, followed by ASIC synthesis , enabling lightweight and secure hardware authentication with enhanced uniqueness, entropy, and reliability.

asic fpga rtl verilog xilinx uart vlsi basys3 puf gatelevel securehardware logicsynthesis

Updated Feb 17, 2026
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ee23b020 / Image-Enhancement-using-Verilog

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Implemented image processing in Verilog by converting BMP (Bitmap) image data into hex format and using FSMs (Finite State Machines) to perform brightness adjustment and color inversion. Verified synthesizability of the design using Yosys synthesis tool to ensure hardware compatibility.

verilog logicsynthesis