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1. Image-Enhancement-using-Verilog Image-Enhancement-using-Verilog Public

   Implemented image processing in Verilog by converting BMP (Bitmap) image data into hex format and using FSMs (Finite State Machines) to perform brightness adjustment and color inversion. Verified s…

   Verilog

2. Design-Verification-of-I2C-Communication-Protocol Design-Verification-of-I2C-Communication-Protocol Public

   I2C Master and Slave in SystemVerilog with FSMs handling start, stop, ACK/NACK, and 7-bit addressing over bidirectional SDA/SCL lines; Implemented control for open-drain behaviour, clock generation…

3. Implementation-of-MBFF-for-Low-Power-Clock-Tree-Design Implementation-of-MBFF-for-Low-Power-Clock-Tree-Design Public

   Implemented Multi-Bit Flip-Flops (MBFFs) to replace single-bit flip-flops (SDFFs), targeting reduced clock-network switching power and cell area; Analyzed power, area, and timing trade-offs.

4. Clock-Tree-Characterization-Optimization Clock-Tree-Characterization-Optimization Public

   Optimized Clock Tree by aiming to reduce CT Cell count, improve timing & power - by choosing optimal drive strengths & netlengths.

5. Asynchronous-FIFO Asynchronous-FIFO Public

   Designed 16×8 async. FIFO with modular memory, synchronizers, & full/empty detection for CDC data transfer. Integrated single-bit ECC and pipelined skid buffers for error correction and high-throug…