Add the V2 XBee 3 castellated carrier board

.github/workflows/ci.yml

@@ -35,6 +35,12 @@ jobs:
       - name: Check purchasing BOM (v2)
         run: cargo +1.96.0 run --locked --manifest-path ci/stackup/Cargo.toml -- bom PCB/v2.x/stackup/board.kdl --locked -o /tmp/snips-bom-v2.csv
 
+      - name: Check Stackup design (XBee carrier)
+        run: cargo +1.96.0 run --locked --manifest-path ci/stackup/Cargo.toml -- check PCB/v2.x/xbee-carrier/stackup/board.kdl --locked
+
+      - name: Check purchasing BOM (XBee carrier)
+        run: cargo +1.96.0 run --locked --manifest-path ci/stackup/Cargo.toml -- bom PCB/v2.x/xbee-carrier/stackup/board.kdl --locked
+
       - name: Install KiCad 10
         run: |
           sudo apt-get update
@@ -55,6 +61,12 @@ jobs:
             --stackup ci/stackup/target/debug/snips-stackup-check \
             --plugin-dir stackup-tool/kicad-plugin
 
+      - name: Check PCB sync (XBee carrier)
+        run: |
+          /usr/bin/python3 ci/check_pcb_sync.py PCB/v2.x/xbee-carrier/xbee_carrier.kicad_pcb \
+            --stackup ci/stackup/target/debug/snips-stackup-check \
+            --plugin-dir stackup-tool/kicad-plugin
+
   native-tests:
     runs-on: ubuntu-latest
     steps:

PCB/v2.x/README.md

@@ -77,7 +77,7 @@ files are organized.
 | TLV62569 VOUT | 22µF ceramic | As on V1. TI specifies 10-47 µF |
 | ESP32-S3-MINI-1U 3V3 | 10µF + 100nF + 39pF ceramic | As on V1 |
 | ESP32-S3-MINI-1U EN | 1µF ceramic | With R_EN_PU1, per Espressif |
-| XBee VCC | 10µF + 1µF + 100nF + 47pF ceramic | On the carrier |
+| XBee VCC | 10µF + 1µF + 47pF ceramic | On the carrier, per Digi 90001543 p.52 |
 
 ### Resistors
 | Signal | Value | Notes |

PCB/v2.x/xbee-carrier/README.md

@@ -0,0 +1,60 @@
+# Snips XBee carrier
+
+A 2-layer castellated daughter board that puts a Digi XBee 3 PRO Micro on the V2 controller's underside. It is optional, and V2 runs without it. The mating footprint on V2 is `U_XBEE1`, `XBee_Carrier_Castellated`.
+
+## Board
+
+- **Size:** 22 x 17 mm, 0.8 mm thick, 2 layers. The chamfer clears the MH3 shell post on V2.
+- **Orientation:** the XBee side faces away from V2 and the bottom sits flat on V2's underside. This board's top view matches V2's footprint coordinates directly, and the chamfer shows which way round it goes.
+- **Height below V2:** about 3.2 mm with the module, plus the U.FL plug.
+- **Edge:** 12 plated half holes at 2.54 mm pitch. Order as castellated holes, with a finish that wets well, such as ENIG.
+- **Clearance:** the board uses 0.15 mm in the corridors between the module's pad tips and the castellations (`xbee_carrier.kicad_dru`).
+
+## Assembly
+
+- Reflow on the top side only. The module is MSL 3, so follow Digi's handling rules.
+- Check that nothing is left proud on the bottom. It has no parts, and V2's vias under it are tented.
+- Solder the carrier to V2 by hand, through the 1.7 mm of V2 land that extends past each castellation.
+
+## Electrical
+
+| Part | Value | Purpose |
+|---|---|---|
+| C_XB_47P1, C_XB_1U1 | 47 pF, 1 µF | At pad 2, per Digi 90001543 p.52. 25 V part for the 1 µF, so it keeps its value at 3.3 V |
+| C_XB_10U1 | 10 µF 0402 | Digi's recommended bulk cap. About 4 µF at 3.3 V, and V2's rail is close by |
+| R_XB_RST_PU1, C_XB_RST1, R_XB_RST1 | 10 kΩ, 100 nF, 100 Ω | V2 drives RESET open drain, so the pull-up is here. About 1 ms of reset as the rail rises |
+| R_XB_ATTN_PU1 | 10 kΩ | BOOTMODE shares this pin and must not be low at reset |
+
+Pads 1-6 are CTS, DIN, DOUT, RTS, ON/SLEEP and RESET. Pad 7 is SLEEP_RQ, 8 GND, 9-10 3V3, and 11-12 GND. Names match V2's nets.
+
+## Layout rules
+
+- No top-side copper under the module, and no copper or vias at its three RF test points (Digi 90001543 p.58). The `XB3-24Z8UM` footprint carries both as rule areas. Signals cross under the module on the bottom layer. The top-side rule stops 0.5 mm short of the module's edge, so pads can reach their vias.
+- Test point positions come from the bottom view on p.34, since the manual has no Micro keepout drawing.
+- The 3D model is Digi's `XB3-UFL-MMT.STEP`.
+
+## Checks
+
+```
+stackup check PCB/v2.x/xbee-carrier/stackup/board.kdl
+```
+
+CI checks the design, the BOM and the PCB sync. Sync with the Stackup KiCad plugin after any KDL change.
+
+## Production
+
+Files are in `production/`, built from this board: `jlcpcb/` holds the order set as `Snips_XBee_Carrier_1_0.zip` with its BOM and positions, and `gerbers/`, `placement/` and `bom/` hold the separate exports. Regenerate them after any board change.
+
+When ordering:
+
+- Select castellated holes. The job file marks the board as castellated, and there are 12 half holes on the two long edges.
+- Use 0.8 mm thickness and ENIG. The board file's copper finish is unset, so choose this in the order.
+- The XBee has no JLC stock, so plan to consign XB3-24Z8UM modules. Mouser and DigiKey stock it.
+- Blue solder mask, to match V2.
+
+## Bench checklist
+
+1. Before soldering to V2, meter for shorts between 3V3 and GND, and between neighbouring castellations.
+2. After soldering, check each of the 12 joints for continuity to its V2 net.
+3. Confirm UART traffic, CTS, SLEEP_RQ and ON/SLEEP, then reset, then join a droid's network.
+4. Repeat V2's power-off test with the carrier fitted, since it adds capacitance to the rail.

PCB/v2.x/xbee-carrier/fabrication-toolkit-options.json

@@ -0,0 +1 @@
+{"ARCHIVE_NAME": "Snips_XBee_Carrier_1_0", "EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": true, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": true, "OPEN BROWSER": true, "BACKUP_OPT": true}

PCB/v2.x/xbee-carrier/fp-lib-table

@@ -0,0 +1,5 @@
+(fp_lib_table
+	(version 7)
+	(lib (name "Xbee3") (type "KiCad") (uri "${KIPRJMOD}/libraries/Xbee3.pretty") (options "") (descr "Digi XBee 3 land patterns"))
+	(lib (name "SnipsControllers_Custom") (type "KiCad") (uri "${KIPRJMOD}/libraries/SnipsControllers_Custom.pretty") (options "") (descr "Snips Controllers custom footprints"))
+)