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Add the V2 XBee 3 castellated carrier board - #105

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thePunderWoman merged 1 commit into
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pcb-v2-xbee-carrier
Nov 2, 2026
Merged

thePunderWoman merged 1 commit into
mainfrom
pcb-v2-xbee-carrier

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@thePunderWoman thePunderWoman commented Nov 2, 2026 •

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Adds the optional daughter board that puts a Digi XBee 3 PRO Micro on the V2 controller's underside. V2 runs without it. The design is in PCB/v2.x/xbee-carrier/, and its README covers assembly, ordering and bring-up.

Board

Size 22 x 17 mm, 0.8 mm, 2 layers, about 3.2 mm below V2 plus the U.FL plug
Mating 12 plated half holes at 2.54 mm pitch, soldered by hand to V2's U_XBEE1 lands
Module XB3-24Z8UM, U.FL at the chamfer end
Parts 47 pF and 1 µF at pad 2, 10 µF, RESET pull-up and RC, ATTN/BOOTMODE pull-up

The XBee side faces away from V2, so this board's top view matches V2's footprint coordinates directly.

Layout

  • Signals cross under the module on the bottom layer. There is no top-side copper under the module, and nothing at its three RF test points (Digi 90001543 p.58), apart from short pad stubs and one ground link within about 1.5 mm of the module's edge.
  • The XBee footprint comes from the V2 history, with its courtyard redrawn to the module's real outline so the caps can sit beside pad 2.
  • The board uses a 0.15 mm clearance rule in the corridors between the module's pad tips and the castellations.
  • Ground is continuous across both layers and does not rely on the module's internal plane.

Verification

  • All 12 edge pads match V2's land positions and net names, compared from both board files.
  • DRC: 0 violations, 0 unconnected. All 41 netlist nodes match the pads, and sync is clean.
  • stackup check: 0 errors. bom_check: 8 lines, 0 problems.
  • CI now checks this board's design, BOM and PCB sync.

Decisions to review

  • 10 µF is an 0402, so about 4 µF at 3.3 V. Digi lists it as recommended, with no proximity rule, and V2's rail is close by.
  • No 100 nF on VCC. Digi does not ask for it, so V2's README is updated.
  • Copper finish: the board file leaves it unset. Choose ENIG when ordering.

Related

The carrier adds capacitance to V2's rail, which reduces the power-off margin. #104, now merged, raised C_LATCH_FB1 to 1 µF to cover that.

Not covered

  • Nothing here has been on real hardware. The README has a bench checklist, including repeating V2's power-off test with the carrier fitted.
  • The RF test point positions come from Digi's bottom-view drawing on p.34, since the manual has no Micro keepout drawing.
  • V2 firmware still needs the UART transport.

🤖 Generated with Claude Code

A 22 x 17 mm, 0.8 mm, 2-layer daughter board that puts an XB3-24Z8UM on
the V2 controller's underside, soldered to its U_XBEE1 lands through 12
plated half holes. V2 runs without it.

It carries Digi's decoupling at pad 2, the RESET pull-up and RC, and the
ATTN/BOOTMODE pull-up. Signals cross under the module on the bottom
layer, so the top side stays clear of copper under the module and at its
RF test points, per Digi 90001543 p.58.

Add the design, layout, production files and CI checks. Drop the 100 nF
from V2's list of carrier decoupling, since Digi does not ask for it.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
@thePunderWoman
thePunderWoman merged commit 59d62fe into main Nov 2, 2026
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thePunderWoman deleted the pcb-v2-xbee-carrier branch November 2, 2026 04:09
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