[thePunderWoman]

Adds power-off margin to the V2 latch, with or without the XBee carrier.

Why

The carrier takes the 3V3 rail from about 36 µF to about 47 µF nominal. A heavier rail collapses more slowly, so RXD0's returning pull-up has longer to act at power-off. With 470 nF, the worst-case margin fell to about 0.03 V.

Change

C_LATCH_FB1 goes from 470 nF to 1 µF, using the CL10A105KB8NNNC (C15849, JLC Basic) already on the board. It sits on the same 0603 pads, so there is no layout change, and the BOM loses a line.

latch_v2_sim.py now runs at the carrier's 48 µF rail, the harder case.

Results

Worst case at a 5 mA load, with both capacitors at their tolerance extremes and a 30k pull-up. Margin is how far the gate stays below threshold.

Board	Rail	470 nF	1 µF
No carrier, derated	25 µF	0.27 V	0.62 V
No carrier, nominal	37 µF	0.13 V	0.46 V
With carrier, nominal	48 µF	0.03 V	0.34 V

The cost is timing:

	470 nF	1 µF
Press to turn on, normal cell	117 ms	168 ms
Press to turn on, flat cell, worst case	292 ms	399 ms
Power-off, worst case	About 2.0 s	About 2.6 s

Verification

• The only functional board change is C_LATCH_FB1's value. Stackup Source line numbers also moved.
• All 11 copper, mask, paste, silk and outline gerbers match main.
• DRC: 0 violations, 0 unconnected. Sync is clean. bom_check: 44 lines, 0 problems.
• latch_v2_sim.py passes all 47 checks, and latch_sim.py passes. Neither runs in CI.

Not covered

These are simulated margins. The capacitor bias derating is an estimate, and the buck is a behavioural model. Bring-up still includes at least 20 power-offs on USB and on battery.

🤖 Generated with Claude Code