Repository navigation
V2 PCB: move PWR_HOLD to IO3 so it holds through USB uploads - #101
Merged
Merged
Conversation
A bench test on V1 hardware showed that IO42's digital-pad hold does not survive the USB reset that ends every upload, so the board would lose power mid-upload. IO3 is an RTC pad, and its hold lasted through a full upload with the pin still high. IO3 has no reset pull, so the power-off protection stays, its strap is ignored at default eFuses, and its power-up glitch is low only, which D_OR2 blocks. XBEE_RESET stays on RXD0. The route to pad 7 is shorter and adds no vias. Regenerate the production files. Co-Authored-By: Claude Opus 5.5 <[email protected]>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Fixes the blocker called out in #100. The V2 board on
mainwould lose power during a USB upload.Bench result
Tested on V1 hardware with a firmware build that holds a pin high and logs whether the hold survives each reset.
0x0c)0x15)Changes
Why IO3
ESP32-S3 datasheet v2.2:
Firmware impact
V2 firmware must call
gpio_hold_enon IO3 andgpio_hold_disbefore powering off.lightSleepFor()must not release the hold, unlike V1's version.Verification
bom_check: 43 lines, 0 problems. The BOM is unchanged.latch_sim.pypasses, andlatch_v2_sim.pypasses all 33 checks. V2 PCB: move PWR_HOLD to IO42 and apply review fixes #100 said 32, which was a miscount. Neither runs in CI.Not covered
IO3 was unconnected on V1, so it was tested with no load. On V2 it drives D_OR2 and the latch gate, which draw very little current. The first USB upload at bring-up confirms it, because the board either stays on or it does not. If it fails, the fallback is swapping PWR_HOLD to RXD0.
🤖 Generated with Claude Code