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V2 PCB: give the power latch hysteresis and hold it from RXD0 - #102
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IO3's gpio_hold survived a USB upload on V1 hardware, but it leaves the latch depending on firmware, and it was only tested with no load. Move PWR_HOLD back to RXD0, whose pull-up holds the latch through any reset or upload with no firmware help, and put XBEE_RESET on IO42. IO3 goes back to unconnected. That pull-up returns as the rail collapses at power-off, with the gate sitting at threshold, so the latch needs hysteresis. C_LATCH_FB1 (470 nF, PWR_EN to gate) kicks the gate clear as PWR_EN falls. It also couples a rising gate back into PWR_EN, which restarts the board at the capacitor tolerance extremes with a 100k pull-down, so R_PWR_EN_PD1 is now 22k. Rewrite latch_v2_sim.py around this behaviour, with 47 checks, and regenerate the production files. Co-Authored-By: Claude Opus 5.5 <[email protected]>
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Makes the V2 power latch behave in every state, with no firmware dependency. Builds on #101 and reverses its pin choice.
Why
gpio_holdsurvived a USB upload on V1 hardware, where IO42's did not, but a firmware bug could still drop power, and it was only tested with no load.Changes
C_LATCH_FB1 is on the bottom at (137.4, 80.8), below the two transistor courtyards. No new vias, and no existing parts moved.
Bigger C_LATCH_G1, extra series diodes and pull-downs on the hold line were simulated and do not fix the re-latch.
Behaviour changes
gpio_holdneeded. Drive RXD0 high at boot and low to power off, and never start UART0 on it.Simulation
scripts/spice/latch_v2_sim.pyis rewritten around this behaviour, with 47 checks, all passing:latch_sim.pyalso passes. Neither runs in CI.Verification
stackup check: 0 errors, with the known LED 3.3 V note.bom_check: 45 lines, 0 problems.Not covered
These are simulated margins, not measured ones. C_LATCH_FB1 has never been on real hardware, the buck is a behavioural model, and the datasheet gives only a typical pull-up, so 30k-100k is a deliberately wide spread. The model leans pessimistic: it restarts the circuit without C_LATCH_FB1 at every load, while V1 stayed off about 10 of 10 on the bench.
Bring-up now includes at least 20 power-offs on USB and on battery, scoping
PWR_ENandPWR_LATCH_G.BAT54W-7-F sourcing with PCBWay is still open.
🤖 Generated with Claude Code