[thePunderWoman]

Review fixes for the V2 board, ahead of ordering.

Do not order until this passes

ROM download mode has not been shown to keep the gpio_hold_en state. To test on V1: hold IO42 with gpio_hold_en(42), run a USB upload, and meter the pin. If the state does not survive, swap PWR_HOLD back to RXD0 and regenerate production.

Changes

Power latch

• PWR_HOLD moves to IO42 and XBEE_RESET to RXD0. IO42 has no reset pull (ESP32-S3 datasheet Table 2-1), while RXD0's pull-up could re-latch the board as the rail collapses at power-off.
• C_LATCH_G1 is now 1 µF, so the latch rides through a short reset.
• R_INV_BASE1 and R_INV_PU1 are now 220 kΩ, which cuts the off drain to 36-57 µA from the resistors alone.

Layout

• C_VSYS1 is added at the ADC pin.
• The buck input cap and feedback divider now sit beside the IC.
• Seven of the eight power vias are doubled, and six GND stitching vias are added at the module.
• Zone clearance is 0.25 mm.

BOM

• C_3V3_1/2/3 are renamed C_MCU_1/2/3, because PCBWay read "3V3" in the designators as a voltage rating.
• Every BOM line now carries MPN, maker, package and details, and all capacitor MPNs have a rated voltage.

Simulation

• scripts/spice/latch_v2_sim.py is new, with 32 checks: battery insertion, USB hot-plug, press time, power-off, reset ride-through at 1 µF and at an estimated 0.55 µF, insertion with the ESD diodes into the dead rail, and a press surviving until firmware drives PWR_HOLD.

Firmware impact

V1 firmware must not run on this board, because the pin map differs. V2 firmware must:

• Call gpio_hold_en(IO42) after driving it high, and gpio_hold_dis(IO42) before powering off.
• Drive PWR_HOLD early in boot. The shortest press that stays on depends on it, simulated at 0.1-0.2 s on a normal cell and up to about 0.4 s on a flat one.
• Keep a watchdog running, since there is no reset button.

A blank board needs the power button held through its first flash.

Verification

• DRC: 0 violations, 0 unconnected. All 279 netlist nodes match the pads, and sync is clean.
• stackup check: 0 errors, with the known LED 3.3 V note. bom_check: 43 lines, 0 problems.
• Gerbers match a fresh export of this board on all 11 layers.
• latch_sim.py and latch_v2_sim.py pass. These do not run in CI.

Not covered

• The buck and charger have no SPICE models, so those figures are hand calculations.
• The 350 ms boot time in the press check and the 0.55 µF derating are estimates until measured.
• The hall sensor's stray field from the stick still needs a bench test.
• BAT54W-7-F has almost no distributor stock. PCBWay sourcing is still open.

production/Snips_2_0.zip and production/netlist.ipc are local duplicates of the jlcpcb/ files and are left out on purpose.

🤖 Generated with Claude Code