🎓 Undergraduate @ Nanjing University of Posts and Telecommunications
📚 Major: Electronic Science and Technology
📍 Nanjing, China
- HDL: Verilog HDL, FPGA Development (Vivado / ISE)
- EDA Tools: Multisim, MATLAB, Origin, CAD
- Programming: C Language
- Office: Word, Excel, PPT, Feishu
- Creative: Photoshop, Premiere
- 🔢 Dynamic Segment Display (Verilog) — FPGA-based 7-segment display with state machine control
- 🕐 Digital Clock (Verilog) — 24小时制数字时钟，6位数码管显示
Electromagnetics · Digital Circuits · Signals & Systems · Analog Electronics · Circuit Analysis · Linear Algebra