-
University College London
- London
- in/yijie-yu-ba53b6232
Highlights
- Pro
Pinned Loading
-
-
rfsoc4x2_ernic
rfsoc4x2_ernic Public100G RDMA (RoCE v2) on RFSoC 4x2 with the AMD ERNIC IP: host RDMA WRITE/READ to PL DDR4 at 98 Gbit/s, byte-exact, Linux rdma-core host
Verilog
-
rfsoc4x2_mts
rfsoc4x2_mts PublicBare-metal multi-tile sync on RFSoC 4x2 (JTAG, no PYNQ) + chirp-training skew estimation with sub-sample resolution and sample-accurate alignment: 4 GSPS two-channel loopback, skew ~100 -> -1.00 (M…
C
-
rfsoc_ofdm
rfsoc_ofdm PublicForked from strath-sdr/rfsoc_ofdm
Fork of strath-sdr/rfsoc_ofdm + bare-metal OFDM link on RFSoC 4x2 (JTAG, no PYNQ): H.264 video over DAC_B -> ADC_B at 5.98 / 11.83 / 23.55 Mb/s (BPSK / QPSK / 16-QAM)
VHDL
-
rfsoc_qsfp_offload
rfsoc_qsfp_offload PublicForked from strath-sdr/rfsoc_qsfp_offload
Fork of strath-sdr/rfsoc_qsfp_offload + PL-only 100GbE UDP echo on RFSoC 4x2 (JTAG, no PYNQ): 4K400 video loopback at 79.77 Gbit/s each way, 4000/4000 frames byte-exact
C
If the problem persists, check the GitHub status page or contact support.