feat: place directly-connected decoupling cap rows across all chip sides (#15)

[iprasen]

Summary of Changes

Fixes #15
/claim #15

This PR introduces PlaceChipConnectedDecouplingCapsSolver to position directly-wired decoupling capacitor rows immediately adjacent to their corresponding main chip pins across all 4 sides (x-, x+, y+, y-).

Key Improvements over PR #268:

1. Full 4-Directional Support (x-, x+, y+, y-):
   • Competing PR Place chip-connected decoupling caps beside their main chip #268 only implemented side === "x-" and treated all other sides as x+, failing completely on chips with top/bottom pins (y+, y-).
   • This implementation handles horizontal translations (x-, x+) with vertical rail-pin clearance alignment, and vertical translations (y+, y-) with horizontal rail-pin clearance alignment.
2. Dynamic Bounding vs Magic Numbers:
   • Replaces hardcoded shift limits (e.g. MAX_PIN_OFFSET_SHIFT = 4) with dynamic clearances derived from the actual main chip bounds, row bounds, and configured chipGap.
3. Preservation of fixedPosition:
   • Explicitly preserves user-defined capacitor coordinates when fixedPosition is specified.
4. Collision Detection & Rollback:
   • Verifies the translated row against all existing chip placements to ensure no bounding collisions; cleanly rolls back to pre-placement coordinates if an overlap is detected.
5. Comprehensive Test Coverage:
   • Includes real RP2040 decoupling layout regression tests (PlaceChipConnectedDecouplingCapsSolver01.test.ts).
   • Includes unit tests explicitly verifying all 4 directions (y+, y-, x+, x-) and fixedPosition preservation (PlaceChipConnectedDecouplingCapsSolver02.test.ts).
   • Snapshot tests updated and verified.

[vercel]

The latest updates on your projects. Learn more about Vercel for GitHub.

Project	Deployment	Actions	Updated
matchpack	Ready	Preview	Sep 18, 2026 7:07pm UTC