Align parallel branches and shared jumper in SI7021 layout

[ikoomm]

The SI7021 example from #11 still scatters R1, R2 and SJ1 on current main. This adds a placement phase that puts the two branches in a parallel row beside their common chip, with the shared three-pin bridge beyond them.

Recognition uses connectivity and pin geometry, independent of reference names. The pass checks both sides of the row, allowed rotations and component clearance; fixed members, extra strong connections and obstructed candidates retain their incoming layout. U1 and C2 remain unchanged in the supplied example. This changes component placement, not wire routing.

Before	After

Validation:

• 14 focused tests passed, including the full SI7021 pipeline, rotated inputs, renamed identifiers, fixed positions, restricted rotations, obstacles and unrelated connectivity.
• Ran the pipeline with and without the new phase on 52 repository JSON examples: all solved in both runs. Only R1, R2 and SJ1 changed in SI7021; the other 51 layouts were identical.
• Full CI passed: 124 tests passed, 0 failed across 71 files; type checking, formatting and preview deployment passed. Local ESM/declaration build also passed.

Closes #12.

/claim #12

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Project	Deployment	Actions	Updated
matchpack	Ready	Preview	Sep 9, 2026 3:32am UTC

[ikoomm]

Hi, this is ready for review for #12. The SI7021 before/after comparison is in the description; all CI checks pass, including 124 tests. Could you confirm whether this placement approach meets the bounty scope, or identify any adjustment needed before merging? Thank you.