xadc

Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.

This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent.

Artix-7 RTL DAQ with FSM control, dual-FIFO buffering, XADC, UART/CRC-16, and shared-I²C arbitration; validated in a 2-hour hardware run.

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

Interactive real-time 1 MSPS Oscilloscope dashboard and Python package for PYNQ boards with Digilent AD3 wave generator integration.

Basys 3 FPGA digital oscilloscope in VHDL using XADC + BRAM + VGA waveform display. (Chosen as Best Project in 2024-2025 Ap)

Hog-managed Vivado hardware overlays for XADC DMA streaming on PYNQ boards. Delivers versioned .bit and .hwh release artifacts for software applications.

Delay vs. die temperature on an Artix-7: I/O and LUT ring oscillators, fabric heaters, XADC telemetry (Opal Kelly XEM7310)

Six self-contained Verilog projects on the Digilent Basys 3 (Artix-7 XC7A35T): PicoBlaze + PmodOLED system, XADC-to-Arduino SPI bridge, PS/2-keyboard-to-UART stack, soft-core CPU, traffic-light FSM, 16x2 LCD driver.