tablegen

A language server for TableGen and a VSCode extension

Tablegen bindings for Rust

MLIR Extension for Zed

My notes on TableGen along with code samples as a first step towards writing compilers with MLIR. The official TableGen documentation is thorough and highly technical — a great reference, but it can be daunting for newcomers.

Generate assemblers from LLVM's TableGen ISA descriptions

Zero-setup hands-on MLIR tutorial for newbies

Process and design documentation for LLVM and LLVM-MOS features

Unified pure-CPU compute engine covering MSC2020 math, graphics & quantum physics. Powered by TableGen, uops silicon simulation, and autonomous SFVM/sfGC runtime, it delivers multi-limb emulation (F8-F256, I/U8-U256) and SIMD steering across AVX10.2/512/APX/AMX, SVE2, and RVV with hardware port contention modeling and LLVM ORCJIT.

A complete visual teardown of LLVM 23, taught from zero, where you run the real optimizer in a notebook, modify it with a pass plugin in ten seconds, and a solver proves whether the optimization you wrote is correct. Blueprints generated from TableGen, and a conformance scorecard attached.

An out-of-tree MLIR dialect for an NPU with a software-managed scratchpad. Explicit DMA, scratchpad-aware verifiers, and passes for fusion, tiling and double buffering.

TableGen grammar for tree-sitter

Emacs major mode to LLVM TableGen

A from-scratch deep learning compiler: it lowers trained ONNX models through two custom MLIR dialects and a full optimization pipeline to a binary instruction stream for a simulated edge NPU, then runs them in a cycle-costed simulator validated against onnxruntime.