Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

This is a basic 5 stage pipelined RV32IM based ISA following CPU core

Toolkit for collecting and exploring logs using pipelined query lanaguage and sqlite.

O(log k) Parallel FHE Conversion IP package featuring pipelined SystemVerilog RTL and Header-Only C++ Library. Designed to accelerate cryptographic pipelines by removing the sequential RNS bottleneck.

Oracle Advanced PL/SQL

Cached 5-stage Pipelined RV32I Processor (Team 19). Supports full RV32I base instructions and features a 2-way set-associative data cache. Highest verified milestone (Stretch Goals 1, 2, 3).

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.

A five-stage pipelined RV32IM core with hazard forwarding and machine-mode traps, verified with RISC-V Formal and Spike lockstep co-simulation, booting FreeRTOS and running CoreMark on a Basys 3 FPGA.