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line-buffer

Here are 4 public repositories matching this topic...

nk12U / Sobel-Filter-FPGA

FPGA-based Sobel Filter Edge Detection

image-processing verilog-hdl sobel-filter line-buffer

Updated Jul 13, 2025
Verilog

electricalgorithm / introduction-to-VHDL-projects

VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.

mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver

Updated May 30, 2022
VHDL

Arsenico22 / 2D_Isotropic_Convolution_Core

2D Isotropic Convolutional Accelerator IP Core.

fpga vhdl image-processing edge-detection 2d-convolution line-buffer

Updated Oct 13, 2026
VHDL

ahmedbadwy77 / sscs26-cnn-accelerator

Streaming N-by-N CNN convolution accelerator on Xilinx Zynq-7020 – 50 LUT / 9 DSP / 0 BRAM / 464 MHz at 2.155 ns / FOM 0.01550 – IEEE SSCS Egypt 2026 Student Design Competition (Team FlipFlopers, Cairo University)

fpga rtl verilog vivado fixed-point modelsim cnn-accelerator edge-ai zynq-7020 line-buffer dsp48e1 ieee-sscs

Updated Sep 25, 2026
Verilog

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