librelane

ASIC implementation flow infrastructure, successor to OpenLane

A novel Design-for-Test flow using LibreLane

A Customized ASIC framework for Retro Stuff

KianV GF180 ASIC runs ulinux, linux and XV6

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.

FazyRV Hachure is a System on Chip that integrates seven different variants of the bit-serial FazyRV RISC-V core in one chip for testing and research purposes.

Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation

AI/LLM-assisted circuit design using opensource tools

ASIC Design Flow of Signed 8x8 Booth-Wallace Multiplier (Radix-4)

Chipathon 2026 workshop padring fork of wafer-space/gf180mcu-project-template - adds a workshop slot mirroring JuanMoya/padring_gf180 as a native LibreLane slot.

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

Simple Systolic array implementation

Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.

Tiny Tapeout TTSKY26c APB I2C master/slave core with FIFO-backed byte host bridge, IRQ handling, and pin-level BFM regression.

Sovryn KAN NPU V2 SG13G2 final freeze with template-native design sources, signoff evidence, and Prometheus v16 signoff-copilot analysis.

Open-source ASIC flow laboratory focused on LibreLane, OpenROAD, Yosys, and open silicon workflows.

Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.

Area-optimized 1x1 SKY130 Tiny Tapeout game design with 640x480 VGA, QSPI PSRAM, dual controllers, and RTL/gate-level verification.

1x2 SKY130 Tiny Tapeout game design with 640x480 VGA, QSPI PSRAM, dual controllers, cocotb verification, and RTL-to-GDS signoff.