Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
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May 5, 2022
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ic-design-project
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This system manages ALU and register file operations based on commands received via UART RX. It operates across two clock domains—one for general processing and another for UART communication. Key functions include executing arithmetic, logic, and data synchronization tasks, with results sent back through UART TX
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Dec 17, 2025 - SystemVerilog
Wa'el Engineering Project Repository
css html image-processing assembly-language-programming 3d-models color-recognition ir-sensors ai-algorithm printed-circuit-boards fpga-programming ic-design-project line-following-robot
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Jan 29, 2026 - Python
Build two simple RV32I cores that share one data memory through a simplified invalidation-based coherence mechanism, wrap it on a bus (AXI4-Lite or AHB-Lite), simulate it (directed + UVM), synthesize it, run it through a physical-design flow, and boot it on an FPGA that shows coherence events on UART/LEDs.
processor rtl verilog coherence systemverilog uvm risc-v rv32i ic-design ic-design-project asic-design uvm-verification
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Sep 15, 2026 - Verilog
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