de10-standard

🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

FPGA实验用DE10-Standard开发板引脚表

Copy of: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1081

SoC and Embedded Linux

Copy of: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1081

VendingMachine is a Verilog implementation of a finite-state vending machine controller that accepts coins, handles product selection, dispenses items and change, and exposes a testbench-friendly RTL for simulation and FPGA synthesis using the DE-10 FPGA Board.

SoC FPGA-based solar power prediction and anomaly monitoring system on DE10-Standard.

DE10-Standard Cyclone V SoC Ethernet controller with PC and Android TCP clients, HPS Linux, PIO bridge access, and HEX display output.

Native macOS schematic editor, simulator and Quartus-style compiler for Cyclone V / DE10-Standard digital-logic labs. Not affiliated with Intel or Altera.

Portfolio-ready Typst/Touying slide deck for the DE10-Standard SoC Ethernet project with visual release assets.

FPGA-based edge detection with salt-and-pepper denoising was successfully implemented on the DE10-Standard board, and results were displayed on a VGA display.

DE10-Standard/SCOMP switch-counter project with a custom memory-mapped VHDL peripheral. Source subset; full board integration files pending.

FPGA Matrix Multipler for DE10 Standard FPGA Board

Handwritten digit recognition in VHDL for DE10-Standard: quantized neural network, VGA drawing, PS/2 input, Quartus project, and self-checking testbenches.

Pokémon-inspired VGA arcade game in SystemVerilog for the DE10-Standard FPGA