All pull requests

Pull requests

• [Transform] Ensure import C source ends with a newline

  #3289·jjppp opened Sep 27, 2026Contributor·

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• [BugFix][CUDA] Keep warp-specialized stages until moved non-TMA copies are consumed

  #3288·ghostrider0470 opened Sep 27, 2026·

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• [CUDA] SM120 block-scaled register-A GEMM: unroll K atoms and load scales once per atom

  #3286·ghostrider0470 opened Sep 27, 2026·

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• feat(cuda): support NVRTC device compilation with TVM-FFI

  #3285·ZenAlexa opened Sep 26, 2026Contributor·

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• [CUDA] Reject conflicting SM120 scale fragment layouts

  #3284·LeiWang1999 opened Sep 26, 2026Member·

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• [Tool] Add TIRX source-span visualization

  #3282·CeleNewYear opened Sep 25, 2026·

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• [CPU][Windows] Fix JIT shared library compilation and exports

  #3281·sepcnt opened Sep 25, 2026Contributor·

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• [Bugfix] Fix candidate buffer overflow in deepseek_v32 topk selector

  #3280·liuyun7345 opened Sep 25, 2026·

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• [Compiler] Unify async data staging and transfer-aware lowering

  #3279·sepcnt opened Sep 24, 2026Contributor·

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• [CUDA][Transform] Expose SIMT im2col loads before scheduling

  #3275·sepcnt opened Sep 24, 2026Contributor·

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• [BugFix][CMake] Keep an SDK path given through the backend environment variables

  #3268·FeathBow opened Sep 21, 2026·

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• [Transform] Add tl.LowerMagicDiv: host-precomputed magic division for dynamic-shape divisors

  #3267·penguin-wwy opened Sep 21, 2026Contributor·

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• [CUDA][Transform] Lower launch-invariant integer arithmetic

  #3265·sepcnt opened Sep 21, 2026Contributor·

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• [ROCm] Fuse GLM-5.3 paged k-pool selection

  #3255·andyluo7 opened Sep 19, 2026Collaborator·

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• [ROCm] Add GLM-5.3 paged k-pool logits

  #3253·andyluo7 opened Sep 19, 2026Collaborator·

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• [ROCm] Add GLM-5.3 k-pool decode-tail maintenance

  #3251·andyluo7 opened Sep 19, 2026Collaborator·

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• [ROCm] Add GLM-5.3 k-pool compression and cache write

  #3250·andyluo7 opened Sep 18, 2026Collaborator·

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• [ROCm] Add safe-gated KDA decode example

  #3249·andyluo7 opened Sep 18, 2026Collaborator·

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• [TileIR] Add a CUDA Tile IR execution backend

  #3247·0xtaruhi opened Sep 18, 2026Collaborator·

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• Reject unsupported GEMM dtype combos before CUDA codegen

  #3245·hywosdpl opened Sep 17, 2026·

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• [BugFix][CUDA][RNG] Diagnose rng_rand/rng_rand_float without rng_init

  #3244·0z5a opened Sep 17, 2026·

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• [BugFix][CUDA][RNG] Reject binding the void rng_init result

  #3243·0z5a opened Sep 17, 2026·

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• [BugFix][CUDA][RNG] Derive the default rng_init sequence from the full launch

  #3242·0z5a opened Sep 17, 2026·

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• [BugFix][CuTeDSL] Repair FP4 conversion/store lowering and packed FP4 output shapes

  #3241·0z5a opened Sep 17, 2026·

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• [BugFix] Avoid stale analyzer bindings after parallel loop partitioning

  #3226·sepcnt opened Sep 14, 2026Contributor·

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