[thePunderWoman]

Summary

Bumper button. The bumper was hard to press with one side-firing switch at one end of the top edge. SW_TRIG_DIG2 (Alps SKRTLAE010) mirrors SW_TRIG_DIG1 at the other end, 13.85 mm either side of the centerline, and is wired in parallel on GPIO18 (BTN_TRIG_DIG). Pressing either one does the same thing, so no firmware change is needed. It is added to the Alps locating-peg rule in snips_controller.kicad_dru.

Hall sensor. U_HALL1 changes from an off-board, hand-wired TO-92 (DRV5055A2QLPGM) to a DRV5055A2QDBZR SOT-23 on the bottom of the board under the trigger magnet. It is now machine-assembled (LCSC C266131, Extended).

• The @stackup/sensor/hall/drv5055 library part only has the TO-92 package, so the SOT-23 is a local part, drv5055a2-sot23, in parts.kdl.
• The SOT-23 pin order (1 = VCC, 2 = OUT, 3 = GND) differs from the TO-92's. It is checked against DS SBAS639E Table 4-1 and KiCad's DRV5055A2xDBZxQ1 symbol.

Firmware. The SOT-23 senses the field perpendicular to the board (§6.3.1), so whether the reading rises or falls with a pull depends on which pole faces it. calibrateTrigger used to treat triggerMax < triggerMin as uncalibrated, so a reversed magnet would calibrate normally and then always read 0. It now accepts either direction. Four regression tests are added.

Mounting holes. The top mounting holes moved: MH1 from (123.4, 81.4) to (123.3, 69.2), and MH2 from (151.6, 70.0) to (151.7, 69.2).

Production files. The V1.2 production files are regenerated:

• gerbers and drill;
• Snips_1_2.zip and netlist.ipc;
• placement;
• the PCB BOM, which now has 7× SKRTLAE010 and the U_HALL1 SOT-23 line.

Housekeeping:

• Removes the legacy pre-Stackup PCB/snips_controller.yaml. Its two references now point at PCB/stackup/board.kdl.
• STEP exports move to PCB/step/v1.1 and PCB/step/v1.2, and the KiCad STEP export path points at v1.2.
• The current shell (for the V1.1 board) moves unchanged to shell/v1.1. These are pure renames, plus the Fusion lib.py data path.

Verification

• stackup check --locked: 83 parts, 0 errors, 0 warnings. The 3 notes are the existing, acknowledged ones.
• PCB sync check: 0 changes. The board matches the Stackup design.
• KiCad DRC with zones refilled: 0 violations, 0 unconnected items.
• pio test -e native: 395/395 pass.
• pio run: builds.

Before ordering

• Check U_HALL1 and U_IMU1 pin 1 in JLC's assembly preview. Both are bottom-side parts.
• The ESP32 module sits directly above U_HALL1, and its shield may slightly bend the magnet's field. Calibration should absorb a fixed offset, but check the trigger's range on the first board.

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