[riscv64] tests/ui/float/minmax.rs: assertion left == right failed

Detected by Ruyici:

---- [ui] tests/ui/float/minmax.rs stdout ----

error: test did not exit with success! code=Some(101) so test would pass with `run-fail`
status: exit status: 101
command: cd "/home/jenkins/rust/build/riscv64gc-unknown-linux-gnu/test/ui/float/minmax" && RUSTC="/home/jenkins/rust/build/riscv64gc-unknown-linux-gnu/stage2/bin/rustc" RUST_TEST_THREADS="64" "/home/jenkins/rust/build/riscv64gc-unknown-linux-gnu/test/ui/float/minmax/a"
stdout: none
--- stderr -------------------------------

thread 'main' (180512) panicked at /home/jenkins/rust/tests/ui/float/minmax.rs:14:5:
assertion `left == right` failed
  left: NaN
 right: -9.0
stack backtrace:
   0: __rustc::rust_begin_unwind
   1: core::panicking::panic_fmt
   2: core::panicking::assert_failed_inner
   3: core::panicking::assert_failed::<f32, f32>
   4: minmax::main
note: Some details are omitted, run with `RUST_BACKTRACE=full` for a verbose backtrace.
------------------------------------------

---- [ui] tests/ui/float/minmax.rs stdout end ----

Opening it to track this.

@rustbot

@rustbot label +O-riscv

That means min is implemented incorrectly on riscv, though it looks like LLVM main already fixes this https://godbolt.org/z/M8sqhf58s. Perhaps you can get that cherry-picked onto the LLVM 22 branch?

@folkertdev

Since #153343, Rust intrinsic minnum will be lowered to llvm.minimumnum instead of llvm.minnum, because llvm.minnum non-deterministically returns either NaN or the other value, and the intrinsic has also renamed.

@folkertdev You used llvm.minnum in the example, so the observed difference may not be entirely unexpected, and if you remove -mtriple option, you'll see the same difference on x86 as well.

I suspect this is a RISC-V hardware implementation bug, considering that there have been known reports of defects about floating-point in certain RISC-V hardware, and also RISC-V ISA previously modified the definitions of fmin and fmax instructions in riscv/riscv-isa-manual#75 -- before ISA v2.2 they implement IEEE 754-2008 minNum and maxNum, since ISA v2.2 they implement IEEE 754-2019 minimumNumber and maximumNumber.

Since #153343, Rust intrinsic minnum will be lowered to llvm.minimumnum instead of llvm.minnum, because llvm.minnum non-deterministically returns either NaN or the other value, and the intrinsic has also renamed.

@folkertdev You used llvm.minnum in the example, so the observed difference may not be entirely unexpected, and if you remove -mtriple option, you'll see the same difference on x86 as well.

I suspect this is a RISC-V hardware implementation bug, considering that there have been known reports of defects about floating-point in certain RISC-V hardware, and also RISC-V ISA previously modified the definitions of fmin and fmax instructions in riscv/riscv-isa-manual#75 -- before ISA v2.2 they implement IEEE 754-2008 minNum and maxNum, since ISA v2.2 they implement IEEE 754-2019 minimumNumber and maximumNumber.

Thanks for the excellent explanations. I confirm this bug is a false positive. I did not reproduce this on another riscv64 hardware.

So close this. Thanks for everyone.

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[riscv64] tests/ui/float/minmax.rs: assertion `left == right` failed #156529

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[riscv64] tests/ui/float/minmax.rs: assertion left == right failed #156529

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yuzibo commented on May 13, 2026

folkertdev commented on May 13, 2026

SpriteOvO commented on May 13, 2026

yuzibo commented on May 14, 2026

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[riscv64] tests/ui/float/minmax.rs: assertion `left == right` failed #156529