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Drop the Armv7-R IFSR domain field and rename its permission fault #238

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Merged
jonathanpallant merged 3 commits into from
Oct 18, 2026
Merged

Drop the Armv7-R IFSR domain field and rename its permission fault #238

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da99357
Drop the Armv7-R IFSR domain field and rename its permission fault
korken89 Oct 18, 2026
51cbed9
Amend CHANGELOG
jonathanpallant Oct 18, 2026
769eb4b
Merge branch 'main' into armv7-r-ifsr
jonathanpallant Oct 18, 2026
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1 change: 1 addition & 0 deletions aarch32-cpu/CHANGELOG.md
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Expand Up @@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Changed

- Fixed the Armv7-R `DfsrStatus` and `IfsrStatus` encodings
- Removed `Ifsr::domain` for Armv7-R
- Fixed `interrupt::free` restoring the IRQ state inverted

## [aarch32-cpu v0.4.0]
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7 changes: 2 additions & 5 deletions aarch32-cpu/src/register/ifsr.rs
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@@ -1,6 +1,6 @@
//! Code for managing IFSR (*Instruction Fault Status Register*)

#[allow(unused)]
#[cfg(any(arm_architecture = "v5te", arm_architecture = "v6"))]
use arbitrary_int::u4;

use crate::register::{SysReg, SysRegRead, SysRegWrite};
Expand Down Expand Up @@ -39,9 +39,6 @@ pub struct Ifsr {
/// AXI Decode or Slave
#[bit(12, r)]
sd: bool,
/// Which domain was being accessed
#[bits(4..=7, rw)]
domain: u4,
/// Status bitfield.
#[bits([0..=3, 10], rw)]
status: Option<IfsrStatus>,
Expand Down Expand Up @@ -167,7 +164,7 @@ pub enum IfsrStatus {
/// Synchronous External abort
SyncExtAbort = 0b01000,
/// Permission fault (MPU)
PermissionFaultFirstLevel = 0b01101,
Permission = 0b01101,
/// IMPLEMENTATION DEFINED fault (Lockdown fault)
Lockdown = 0b10100,
/// Synchronous parity or ECC error
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4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-a32-armv7r-none-eabi.snap
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Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Skipping instruction
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4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-a32-armv7r-none-eabihf.snap
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Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Skipping instruction
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4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-a32-thumbv7r-none-eabi.snap
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Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Skipping instruction
Expand Down
4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-a32-thumbv7r-none-eabihf.snap
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_a32
Skipping instruction
Expand Down
4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-t32-armv7r-none-eabi.snap
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Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Skipping instruction
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4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-t32-armv7r-none-eabihf.snap
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Skipping instruction
Expand Down
4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-t32-thumbv7r-none-eabi.snap
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Skipping instruction
Expand Down
4 changes: 2 additions & 2 deletions aarch32-tests/tests/snapshots/versatileab/prefetch-exception-t32-thumbv7r-none-eabihf.snap
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@ expression: stdout
---
Hello, this is a prefetch abort exception example
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Doing it again
prefetch abort occurred
IFSR (Fault Status Register): Ifsr { sd: false, domain: 0, status: Ok(DebugEvent) }
IFSR (Fault Status Register): Ifsr { sd: false, status: Ok(DebugEvent) }
IFAR (Faulting Address Register): Ifar(0)
caught bkpt_from_t32
Skipping instruction
Expand Down