Shaikra audio support

Documentation/ABI/testing/sysfs-lontium-firmware

@@ -0,0 +1,10 @@
+What:		/sys/bus/i2c/drivers/<driver>/.../firmware
+Date:		July 2026
+KernelVersion:	7.3
+Contact:	Mohit Dsor <[email protected]>
+Description:
+		Read: Returns the current firmware version loaded on the
+		Lontium bridge chip in hex format (e.g. "0x0105").
+
+		Write: Triggers a firmware upgrade of the chip using the
+		firmware file loaded via the firmware loader.

Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml

@@ -21,6 +21,7 @@ properties:
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine
           - qcom,sc7280-inline-crypto-engine
+          - qcom,shikra-inline-crypto-engine
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
@@ -55,14 +56,25 @@ required:
 
 additionalProperties: false
 
+# Do not extend the list.
+# Legacy SoCs are allowed for single clock.
+# New SoCs must provide both clocks and power domains.
 allOf:
   - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,eliza-inline-crypto-engine
-              - qcom,milos-inline-crypto-engine
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - qcom,kaanapali-inline-crypto-engine
+                - qcom,qcs8300-inline-crypto-engine
+                - qcom,sa8775p-inline-crypto-engine
+                - qcom,sc7180-inline-crypto-engine
+                - qcom,sc7280-inline-crypto-engine
+                - qcom,sm8450-inline-crypto-engine
+                - qcom,sm8550-inline-crypto-engine
+                - qcom,sm8650-inline-crypto-engine
+                - qcom,sm8750-inline-crypto-engine
 
     then:
       required:

Documentation/devicetree/bindings/crypto/qcom,prng.yaml

@@ -30,6 +30,7 @@ properties:
               - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
+              - qcom,shikra-trng
               - qcom,sm8450-trng
               - qcom,sm8550-trng
               - qcom,sm8650-trng

Documentation/devicetree/bindings/crypto/qcom-qce.yaml

@@ -54,6 +54,7 @@ properties:
               - qcom,qcs8300-qce
               - qcom,sa8775p-qce
               - qcom,sc7280-qce
+              - qcom,shikra-qce
               - qcom,sm6350-qce
               - qcom,sm8250-qce
               - qcom,sm8350-qce

Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml

@@ -4,19 +4,23 @@
 $id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge
+title: Lontium LT9611(UXC/C/EX/UXD) 2 Port MIPI DSI to HDMI Bridge
 
 maintainers:
   - Vinod Koul <[email protected]>
 
 description: |
-  The LT9611 and LT9611UXC are bridge devices which convert DSI to HDMI
+  The LT9611, LT9611UXC, LT9611C, LT9611EX, and LT9611UXD
+  are bridge devices which convert DSI to HDMI
 
 properties:
   compatible:
     enum:
       - lontium,lt9611
+      - lontium,lt9611c
+      - lontium,lt9611ex
       - lontium,lt9611uxc
+      - lontium,lt9611uxd
 
   reg:
     maxItems: 1
@@ -78,6 +82,16 @@ required:
 
 allOf:
   - $ref: /schemas/sound/dai-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: lontium,lt9611c
+    then:
+      properties:
+        ports:
+          properties:
+            port@1: false
 
 unevaluatedProperties: false
 

Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml

@@ -12,6 +12,15 @@ maintainers:
 
 allOf:
   - $ref: dma-controller.yaml#
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: qcom,shikra-bam-dma
+    then:
+      properties:
+        qcom,vmid: false
 
 properties:
   compatible:
@@ -29,6 +38,8 @@ properties:
           - enum:
               # SDM845, SM6115, SM8150, SM8250 and QCM2290
               - qcom,bam-v1.7.4
+              # Shikra
+              - qcom,shikra-bam-dma
           - const: qcom,bam-v1.7.0
 
   clocks:
@@ -48,7 +59,7 @@ properties:
 
   iommus:
     minItems: 1
-    maxItems: 6
+    maxItems: 7
 
   num-channels:
     $ref: /schemas/types.yaml#/definitions/uint32
@@ -81,6 +92,21 @@ properties:
       Indicates that the bam is powered up by a remote processor but must be
       initialized by the local processor.
 
+  qcom,vmid:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 8
+    items:
+      minimum: 1
+      maximum: 63
+    description:
+      Destination VMIDs of the remote processor(s) that read the per-channel
+      descriptor FIFOs as an AXI master. When present, the driver SCM-assigns
+      each FIFO to these VMIDs so the remote access does not trigger an XPU
+      violation. HLOS is always retained as the source owner and must not be
+      listed. Optional even when the qcom,shikra-bam-dma compatible is
+      present; not valid on any other compatible in this schema.
+
   reg:
     maxItems: 1
 

Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml

@@ -22,7 +22,13 @@ description: |
 
 properties:
   compatible:
-    const: qcom,bam-dmux
+    oneOf:
+      - const: qcom,bam-dmux
+      - items:
+          - enum:
+              # Shikra
+              - qcom,shikra-bam-dmux
+          - const: qcom,bam-dmux
 
   interrupts:
     description:

Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml

@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,shikra-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shikra PCI Express Root Complex
+
+maintainers:
+  - Bjorn Andersson <[email protected]>
+  - Manivannan Sadhasivam <[email protected]>
+
+description:
+  Qualcomm Shikra SoC (and compatible) PCIe root complex controller is based on
+  the Synopsys DesignWare PCIe IP.
+
+properties:
+  compatible:
+    const: qcom,shikra-pcie
+
+  reg:
+    minItems: 5
+    maxItems: 6
+
+  reg-names:
+    minItems: 5
+    items:
+      - const: parf # Qualcomm specific registers
+      - const: dbi # DesignWare PCIe registers
+      - const: elbi # External local bus interface registers
+      - const: atu # ATU address space
+      - const: config # PCIe configuration space
+      - const: mhi # MHI registers
+
+  clocks:
+    minItems: 7
+    maxItems: 9
+
+  clock-names:
+    minItems: 7
+    items:
+      - const: aux # Auxiliary clock
+      - const: cfg # Configuration clock
+      - const: bus_master # Master AXI clock
+      - const: bus_slave # Slave AXI clock
+      - const: slave_q2a # Slave Q2A clock
+      - const: ddrss_memnoc_pcie # PCIe SF MEMNOC clock
+      - const: tile # PCIe tile SYS NoC clock
+      - const: qmip_pcie_ahb # QMIP PCIe AHB clock
+
+  interrupts:
+    minItems: 8
+    maxItems: 9
+
+  interrupt-names:
+    minItems: 8
+    items:
+      - const: msi0
+      - const: msi1
+      - const: msi2
+      - const: msi3
+      - const: msi4
+      - const: msi5
+      - const: msi6
+      - const: msi7
+      - const: global
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    minItems: 1
+    items:
+      - const: pci # PCIe core reset
+      - const: link_down # PCIe link down reset
+
+required:
+  - power-domains
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+    #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie@45e8000 {
+          device_type = "pci";
+          compatible = "qcom,shikra-pcie";
+          reg = <0x0 0x045e8000 0x0 0x3000>,
+                <0x0 0x60000000 0x0 0xf1d>,
+                <0x0 0x60000f20 0x0 0xa8>,
+                <0x0 0x60001000 0x0 0x1000>,
+                <0x0 0x60100000 0x0 0x100000>,
+                <0x0 0x045eb000 0x0 0x1000>;
+          reg-names = "parf",
+                      "dbi",
+                      "elbi",
+                      "atu",
+                      "config",
+                      "mhi";
+          #address-cells = <3>;
+          #size-cells = <2>;
+          ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+                   <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>,
+                   <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>;
+          bus-range = <0x00 0xff>;
+
+          linux,pci-domain = <0>;
+          num-lanes = <1>;
+
+          interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+                       <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+          interrupt-names = "msi0",
+                            "msi1",
+                            "msi2",
+                            "msi3",
+                            "msi4",
+                            "msi5",
+                            "msi6",
+                            "msi7",
+                            "global";
+
+          interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+                          <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+                          <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+                          <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+          interrupt-map-mask = <0 0 0 0x7>;
+          #interrupt-cells = <1>;
+
+          clocks = <&gcc GCC_PCIE_AUX_CLK>,
+                   <&gcc GCC_PCIE_CFG_AHB_CLK>,
+                   <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+                   <&gcc GCC_PCIE_SLV_AXI_CLK>,
+                   <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+                   <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+                   <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>,
+                   <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>;
+          clock-names = "aux",
+                        "cfg",
+                        "bus_master",
+                        "bus_slave",
+                        "slave_q2a",
+                        "ddrss_memnoc_pcie",
+                        "tile",
+                        "qmip_pcie_ahb";
+
+          assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+          assigned-clock-rates = <19200000>;
+
+          interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG
+                          &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+                          <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+                          &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>;
+
+          interconnect-names = "pcie-mem",
+                               "cpu-pcie";
+
+          iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+                      <0x100 &apps_smmu 0x801 0x1>;
+
+          resets = <&gcc GCC_PCIE_BCR>;
+          reset-names = "pci";
+
+          power-domains = <&gcc GCC_PCIE_GDSC>;
+
+          max-link-speed = <2>;
+
+          operating-points-v2 = <&pcie_opp_table>;
+
+          status = "disabled";
+
+          pcie_opp_table: opp-table {
+                  compatible = "operating-points-v2";
+
+                  /* GEN 1 x1 */
+                  opp-2500000 {
+                          opp-hz = /bits/ 64 <2500000>;
+                          required-opps = <&rpmpd_opp_nom>;
+                          opp-peak-kBps = <250000 1>;
+                          opp-level = <1>;
+                  };
+
+                  /* GEN 2 x1 */
+                  opp-5000000 {
+                          opp-hz = /bits/ 64 <5000000>;
+                          required-opps = <&rpmpd_opp_nom>;
+                          opp-peak-kBps = <500000 1>;
+                          opp-level = <2>;
+                  };
+          };
+        };
+    };