Merge Chips-IT contributions to pulp repo - #103
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RiccardoGandolfi wants to merge 42 commits into
Draft
RiccardoGandolfi wants to merge 42 commits into
RiccardoGandolfi wants to merge 42 commits into
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…CLUSTER (updated bender.yml for cluster_icache version)
…pulp-runtime entry in Makefile + added icache def in bender-common.mk
…d pulp-sdk cloning rule to Makefile
…d cv32e40p dependency to use the riscv from AlSaqr (checked out at Astral v1.0) + re-added tb_fs_handler file
…ests and pulp-sdk
…witch between mchan and idma when generating compile script
Clean scripts-bender-vsim-mchan rule Co-authored-by: Yvan Tortorella <[email protected]>
…ate iDMA rtl before top rtl build
Pulp open revival
* Added rule to clone and install main dependencies for Deeploy * Added setup script for Deeploy * Adjusted setup script for Deeploy * Added PULP_OPEN_HOME env var to deeploy setup script * Added rule to build compile script with mchan + fix on L1 size for simpleCNN execution (aligned with sdk and gvsoc) * Updated pulp-sdk commit in top Makefile: pointing to Numpy patch + link.ld realignment * Replaced ssh links with https ones for sdk, gvsoc, deeploy, pulp-runtime and regression-tests * Updated README: Deeploy + gvsoc usage * Updated Deeploy commit in top Makefile + Fixes to vsim scripts to simulate rtl inside Deeploy + minor clean-up from no longer existing .tcl scripts * Updated readme * Updated Deeploy commit in Makefile * Removed base_addr_i from pulp_cluster instance + fix for more control over Bender version in Makefile * Added generate_idma_rule to build_qone rule + updated pulp-runtime commit for QuestaOne fixes * Updated pulp-runtime commit + updated linting command --------- Co-authored-by: RiccardoGandolfi <[email protected]> Co-authored-by: RiccardoGandolfi <[email protected]>
* Updated gvsoc commit in Makefile * Fixing toolchain path in Deeploy setup script * Fixes: updated pulp_cluster commit + gvsoc commit (correct checkout to gvsoc-pulp) + updated deeploy setup script * Updated Bender: new commits for iDMA and pulp cluster + added init rule * Added run -all; quit; commands to run.tcl --------- Co-authored-by: RiccardoGandolfi <[email protected]>
* Updated cluster and iDMA bender entries * Updated burst length parameter for DMAs in pulp cluster instance inside cluster domain * Updated Deeploy commit in Makefile * updated cluster and iDMA commits
…ad + clock gating iDMA drivers (#8) * [MAKEFILE & BENDER] Update to latest pulp-sdk + fix for adv_dbg_if & pulp_soc IPs with newer bender versions * [MAKEFILE & BENDER] Update pulp_cluster commit + fix for iDMA generation in bender > 0.28.0 * fix make init and update .gitignore * [MAKEFILE & BENDER] Update pulp-sdk commit + update cluster peripherals entry in lock file * [MAKEFILE] Update makefile with new rule for iDMA generation: use venv instead of pre-activated micromamba env * [fast preload] Enable fast debug preload mode (active by default) This commit enables the fast debug preload via direct soc_interconnect access (backported from PULPissimo). It is active by default through a USE_FAST_DEBUG_PRELOAD parameter. A follow-up commit should make it cleaner by making it selectable from SDK/Runtime. * [MAKEFILE] Update pulp-sdk commit: update on iDMA drivers for clock gating features --------- Co-authored-by: marchioa <[email protected]> Co-authored-by: Francesco Conti <[email protected]>
…mpy 2.4.1 version * [DEEPLOY] Update deeploy commit in Makefile --> iDMA clock gating is supported * [DEEPLOY & SIM] Add run_gui.tcl script for vsim.gui simulation in Deeploy & pulp-sdk * [DEEPLOY] Update Deeploy commit in Makefile --> .item() fixes in Python * [DEEPLOY] Update deeploy commit after forced re-alignment of chips-it branch
…-core parallel execution mode£
…#18) * [CI] First setup for gitlab CI * [CI] Update sdk and nonfree commits: add venv rule call for python deps in CI * [CI] Update nonfree commit * [SDK] Update sdk commit --> add venv rule for CI * [CI]: Update nonfree and sdk commits --> add multiple test groups to CI + adjust iDMA printfs * [CI] Add fpga stage to CI + update Makefile with init-fpga + nonfree commit * Added rule to clone and install main dependencies for Deeploy * Added setup script for Deeploy * Adjusted setup script for Deeploy * Added PULP_OPEN_HOME env var to deeploy setup script * Replaced ssh links with https ones for sdk, gvsoc, deeploy, pulp-runtime and regression-tests * Updated README: Deeploy + gvsoc usage * Updated Deeploy commit in top Makefile + Fixes to vsim scripts to simulate rtl inside Deeploy + minor clean-up from no longer existing .tcl scripts * Updated readme * Added new JtagIdCode definition for pulp-open * [PULP_VCU118] Updates for xilinx ips + updated defines for fpga flow + updated xilinx_pulp.v and constraints * [PULP_VCU118] Updated hci, hier-icache, pulp_cluster entries with temporary fixes for pulp vcu118 flow * FPGA: updated targets in fpga generation script * FPGA: fixed the pad_jtag_trst value to high in xilinx_pulp.v * [FPGA] Updated the run.tcl script: added a parameter to avoid long delays during update_compile_order step; added a property so that Vivado correctly recognizes XPM macros. * [MAKEFILE] Update pulp_cluster commit + check out to already-deployed iDMA rtl * [BENDER] Update pulp_cluster commit for fpga fix on pulp_soc_defines.sv inclusion * [TB_PULP] Fix to BAUDRATE value --> now printf through UART works when launching tests in pulp-sdk * [FPGA] Updated fpga flow: the verilog_define property is now passed to Vivado through the bender generated script * [FPGA] Add the PULP_FPGA_EMUL define to the synthesis flow * [BENDER] Align some dependencies to pulp_cluster * [BENDER] Update the riscv-dbg IP * [DEEPLOY] Add GCC_INSTALL_DIR variable to deeploy setup script * Revert "[BENDER] Update the riscv-dbg IP" This reverts commit 4dcb239. * [MAKEFILE] Add new target to Makefile for compiling pulp-open with mchan on FPGA * [MAKEFILE] Remove comment from generate_idma_rtl rule * [BENDER] Fix pulp_cluster entry in Bender.lock * [CI] Make fpga CI stage manual only * Delete unused/commented-out code * [CI] Update nonfree commit: remove random iDMA tests --------- Co-authored-by: RiccardoGandolfi <[email protected]> Co-authored-by: RiccardoGandolfi <[email protected]> Co-authored-by: Carlotta Chiarini <[email protected]>
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