feat(flow): run synthesis LEC before floorplan

[Emin017]

What Changed

Default rtl2gds now proves synthesis LEC before physical design, and Yosys LEC reads mapped netlists the same way synthesis writes them.

• Insert LEC (yosys_lec) immediately after SYNTHESIS in build_rtl2gds_flow(). rcx and harden inherit this because they start from that builder. EngineFlow already skips yosys_lec when chaining physical I/O, so Floorplan still consumes Synthesis outputs; a LEC step after Synthesis already uses the synthesis golden netlist.
• In run_lec.tcl, change splitnets -ports from -format __v to -format _ so LEC matches the synthesis final netlist (splitnets -format _ -ports). __v is the internal-net format used earlier in synthesis, and it would make gold/gate port bits disagree (foo_0 vs foo__v0).
• Read gold/gate Verilog with read_verilog -sv -icells after liberty models are loaded, so mapped standard-cell instances stay cells instead of unknown modules.

Resulting default rtl2gds chain:

SYNTHESIS → LEC → FLOORPLAN → PLACEMENT → CTS → LEGALIZATION → TIMING_OPT → ROUTING → DRC → LVS → FILLER → POST_ROUTE_LEC

synthesis_lec already had this post-synth LEC step; this PR turns it on for the physical presets as well.

Scope

Select the areas touched by this PR:

• CLI - command behavior, Typer command surface, output formats, or workspace commands.
• Flow/runtime - workspace lifecycle, EngineFlow, step execution, logs, metrics, or artifacts.
• EDA integration - Yosys, ECC-Tools, DreamPlace, KLayout, PDKs, or native/runtime wrappers.
• Build/package - Nix, PyInstaller, wheels, uv.lock, or release artifacts.
• CI/release - GitHub Actions, version checks, changelog, or release automation.
• Tests/docs only

Runtime And Packaging Impact

• No runtime or packaging impact
• CLI output or machine-readable contract changed
• Workspace layout, flow state, or artifact paths changed
• Native toolchain or wrapper behavior changed
• ecc-tools or ecc-dreamplace dependency changed
• PyInstaller, Nix, or release artifact changed

Notes:

• New workspaces on rtl2gds / rcx / harden gain a lec_yosys_lec step between Synthesis and Floorplan. Existing workspaces keep their persisted step list until reconcile/rebuild.
• Yosys LEC Tcl behavior changes for every LEC run, including synthesis_lec and post-route LEC.
• Docs still describe rtl2gds as SYNTHESIS → FLOORPLAN → .... Tests that pin the exact default step list are not updated in this diff (test/rtl2gds/test_builder.py, test/engine/test_reconcile.py RTL2GDS_STEPS, and any CLI continuation fixtures that hard-code the 11-step rtl2gds chain).

Validation

List the commands you ran. Mark checks that are not applicable as N/A.

• uv run pytest test/
• uv run ruff check chipcompiler test
• uv run ruff format --check chipcompiler test
• PyInstaller smoke: ecc --help, ecc --version, ecc version --json
• Nix smoke: nix run .#cli -- --help
• Manual flow smoke:
• Other:

Skipped checks and reason:

• No tests or lint were run for this description-only request.
• Expected unit failures until the pinned rtl2gds step lists are updated: test_build_rtl2gds_flow_includes_lvs_after_drc and reconcile fixtures that assume Synthesis is followed by Floorplan.
• No full rtl2gds / GCD LEC smoke was run, so mapped-netlist ingest (-icells + port splitnets -format _) is not proven on a real PDK netlist here.
• PyInstaller / Nix packaging is N/A: no CLI surface, lockfile, or release-input change.

Checklist

• I kept the change scoped to ECC.
• I updated docs or user-facing CLI text where behavior changed.
• I included lockfile or version metadata updates when dependencies changed.
• I documented any submodule updates and why they are needed.
• I did not include local caches, virtual environments, or generated build outputs.
• I explained skipped validation and remaining risk.