All pull requests

Pull requests

• Route-throughs, congestion-aware large-design P&R, tested with a 4-lane crypto 6.3–6.9 MH/s miner stretch entry

  #159·jrrk2 opened Nov 3, 2026·

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  12

• xilinx: inverted clock fixes from upstream (YosysHQ/nextpnr#1879)

  #158·cavearr opened Nov 2, 2026·

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  6

• xilinx: time the LUT DI2 input and the LUT-RAM and SRL clock-to-out

  #157·cavearr opened Oct 30, 2026·

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  1

• build: ccache/sccache launcher in CMake; cache compiles and chip databases in CI, optional remote store

  #148·lru49 opened Oct 28, 2026·

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  1

  1

• himbaechel/xilinx: do not bind the source wire of a clock net with no loads

  #142·jrrk2 opened Oct 26, 2026·

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  2

• demos: Vortex GPGPU on the VC707 as a stretch entry

  #140·jrrk2 opened Oct 26, 2026·

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  10

• router1: name the net and wires when the legality check finds stubs

  #139·jrrk2 opened Oct 26, 2026·

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  2

• xilinx: stop regional clock sink walks at GFAN wires

  #118·RossComputerGuy opened Oct 18, 2026·

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  3

• xilinx: retain GTX reference selector nets and emit fabric input enable

  #83·codex-hil opened Oct 10, 2026·

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  4

• xilinx: pack RAM32X2S and RAM32X1S, the missing 32-deep single-port LUTRAMs

  #56·gHashTag opened Sep 29, 2026·

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  17