[ARM] Restore cache information - #292
Open
chaitu236 wants to merge 2 commits into
Open
Conversation
Describe the Cortex-A9 L1 cache geometry and link both CPUs to the shared PL310 L2 cache. Add the L2 cache geometry as well. This allows the generic cacheinfo framework to expose cache size, line size, set count, associativity, and sharing information through sysfs. Assisted-by: Copilot:GPT-5.6-Sol Signed-off-by: Chaitanya Vadrevu <[email protected]>
Released NI ARM software expects cache size attributes in sysfs to be reported as bytes, matching the format provided by older NI kernels. The generic cacheinfo implementation reports sizes with a K suffix, which causes existing LabVIEW CPU information code to interpret a 32K cache as 32 bytes. Add an NI ARM compatibility option that reports cache sizes in bytes and enable it for NI Zynq targets. Other platforms retain the standard generic cacheinfo format. Assisted-by: Copilot:GPT-5.6-Sol Signed-off-by: Chaitanya Vadrevu <[email protected]>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Restore cache information for ARM targets on 6.18 kernel that was previously implemented in 4.14 with 111fd34 and 8bb1a5f which these commits replace.
ARM version of libniCPULib expects raw bytes instead of
32K, etc so add a compatibility commit.WI: AB#3990506
Testing