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Add staged (tiled_reduce_staged) multi-vector MaxSim kernel POC #1200

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90fc533
Add staged (tiled_reduce_staged) multi-vector MaxSim kernel POC
Jun 24, 2026
a27808c
Merge branch 'main' into users/suryangupta/staged_maxsim_kernel
Jul 1, 2026
817c108
Add tiler experimentation
Jul 20, 2026
d9daec5
Add paneled end to end design
Jul 31, 2026
2980950
Improve design as per new feedabcks
Aug 1, 2026
a550ecf
Improve Design
Aug 6, 2026
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47 changes: 47 additions & 0 deletions diskann-benchmark/example/multi-vector-3way.json
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{
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]
}
},
{
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]
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},
{
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}
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}
71 changes: 71 additions & 0 deletions diskann-benchmark/example/multi-vector-f16.json
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{
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20 changes: 20 additions & 0 deletions diskann-benchmark/example/multi-vector-paneled-f32.json
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{
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}
20 changes: 20 additions & 0 deletions diskann-benchmark/example/multi-vector-quant.json
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{
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}
41 changes: 41 additions & 0 deletions diskann-benchmark/example/multi-vector-staged.json
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{
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]
}
20 changes: 20 additions & 0 deletions diskann-benchmark/example/multi-vector-tiled-f16.json
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{
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{ "num_query_vectors": 16, "num_doc_vectors": 64, "dim": 256, "loops_per_measurement": 100, "num_measurements": 50 },
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{ "num_query_vectors": 32, "num_doc_vectors": 32, "dim": 512, "loops_per_measurement": 50, "num_measurements": 50 }
]
}
}
]
}
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