libkernel: slab: fix clippy lint

libkernel/src/memory/allocators/slab/cache.rs

@@ -153,8 +153,8 @@ impl SlabCache {
     ) {
         for (line, slab) in self.caches.iter_mut().zip(slab_alloc.managers.iter()) {
             let mut slab = slab.lock_save_irq();
-            for i in 0..line.next_free {
-                slab.free(line.ptrs[i]);
+            for ptr in line.ptrs.iter().take(line.next_free) {
+                slab.free(*ptr);
             }
             line.next_free = 0;
         }

src/drivers/interrupts/arm_gic_v2.rs

@@ -151,31 +151,31 @@ impl ArmGicV2 {
 
         // 3. Configure all interrupts
         // Set all interrupts to Group 0 (secure)
-        for i in 0..(num_interrupts / 32) {
-            self.dist.IGROUPR[i].set(0); // Group 0 = 0 (secure interrupts)
+        for reg in self.dist.IGROUPR.iter().take(num_interrupts / 32) {
+            reg.set(0); // Group 0 = 0 (secure interrupts)
         }
 
         // Disable all interrupts
-        for i in 0..(num_interrupts / 32) {
-            self.dist.ICENABLER[i].set(0xFFFF_FFFF);
+        for reg in self.dist.ICENABLER.iter().take(num_interrupts / 32) {
+            reg.set(0xFFFF_FFFF);
         }
 
         // Clear all pending interrupts
-        for i in 0..(num_interrupts / 32) {
-            self.dist.ICPENDR[i].set(0xFFFF_FFFF);
+        for reg in self.dist.ICPENDR.iter().take(num_interrupts / 32) {
+            reg.set(0xFFFF_FFFF);
         }
 
         // Set priorities - default all to 0xA0 (medium priority)
-        for i in 0..(num_interrupts / 4) {
+        for reg in self.dist.IPRIORITYR.iter().take(num_interrupts / 4) {
             // Each IPRIORITYR register covers 4 interrupts, 8 bits each
-            self.dist.IPRIORITYR[i].set(0xA0A0_A0A0);
+            reg.set(0xA0A0_A0A0);
         }
 
         // Configure interrupts as level triggered (0)
-        for i in 0..(num_interrupts / 16) {
+        for reg in self.dist.ICFGR.iter().take(num_interrupts / 16) {
             // Each ICFGR register configures 16 interrupts, 2 bits each.
             // 0 = level triggered, 1 = edge triggered.
-            self.dist.ICFGR[i].set(0);
+            reg.set(0);
         }
 
         // 4. Enable Distributor

src/drivers/interrupts/arm_gic_v3.rs

@@ -50,7 +50,7 @@
 }
 
 #[inline(always)]
 fn set_icc_sgi1r_el1(value: u64) {
     unsafe { asm!("msr ICC_SGI1R_EL1, {}", in(reg) value, options(nostack, nomem)) };
 }
 
@@ -191,8 +191,8 @@
         let num_spis = (it_lines * 32).saturating_sub(32) as usize;
 
         // Set all SPIs to Group 1 (non-secure)
-        for i in 1..num_spis.div_ceil(32) {
-            dist.IGROUPR[i].set(0xFFFF_FFFF);
+        for reg in dist.IGROUPR.iter().take(num_spis.div_ceil(32)).skip(1) {
+            reg.set(0xFFFF_FFFF);
         }
 
         // Disable, clear pending, and set default priority for all SPIs
@@ -202,8 +202,8 @@
         }
 
         // Set all priorites to 0 (highest).
-        for i in 8..((num_spis + 31) / 4) {
-            dist.IPRIORITYR[i].set(0);
+        for reg in dist.IPRIORITYR.iter().take((num_spis + 31) / 4).skip(8) {
+            reg.set(0);
         }
 
         // EnableGrp1ns: Enable group 1Ns interrupts
@@ -242,8 +242,8 @@
         sgi_ppi.ICPENDR0.set(0xFFFF_FFFF); // Clear all pending
 
         // Set default priorities
-        for i in 0..8 {
-            sgi_ppi.IPRIORITYR[i].set(0xA0A0_A0A0);
+        for reg in sgi_ppi.IPRIORITYR.iter().take(8) {
+            reg.set(0xA0A0_A0A0);
         }
 
         // 3. Enable the CPU's system register interface to the GIC