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ggml-cpu: skip x86 variants whose register state the OS has not enabled - #246

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alanshurafa wants to merge 3 commits into
handy-computer:mainfrom
alanshurafa:fix/cpu-score-os-xsave-check
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alanshurafa wants to merge 3 commits into
handy-computer:mainfrom
alanshurafa:fix/cpu-score-os-xsave-check

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@alanshurafa

@alanshurafa alanshurafa commented Nov 6, 2026 •

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Summary

Handy no longer fails to load any model on newer AMD processors where Windows hasn't switched on the chip's advanced math features.

  • Zen 5 on Windows: CPUID says AVX-512, but XCR0 = 0x7 (OS has AVX-512 state off).
  • ggml_backend_cpu_x86_score() only checks CPUID, so it picks ggml-cpu-cascadelake.dll; the first 512-bit instruction faults (0xC000001D).
  • Fix: read XCR0 with xgetbv when OSXSAVE is set, and score a variant 0 if the OS hasn't enabled the state it needs (YMM for AVX, opmask + ZMM for AVX-512, tiles for AMX).
  • Machines with everything enabled get the same scores as before.

Scope

  • ggml/src/ggml-cpu/arch/x86/cpu-feats.cpp: the fix.
  • patches/ggml/0004-cpu-x86-score-os-xsave-check.patch + ggml/UPSTREAM: same change as a downstream patch so sync-ggml.sh keeps it.

Related

Fixes cjpais/Handy#2402. Measurements from fakingpescobar-ctrl in that issue.
Not fixed in llama.cpp master yet; open PRs there: ggml-org/llama.cpp#19514, #20388, #20940.

AI Assistance

Code written with Claude Code; I reviewed it.

Validation

Harness compiling patched and original cpu-feats.cpp per variant (MSVC 2022, same GGML_* defines), with XCR0 injected:

  • Intel host, XCR0 = 0xE7: all scores unchanged.
  • Zen 5 CPUID from the issue, XCR0 = 0x7: AVX-512 variants score 0, best becomes alderlake (was zen4).
  • OSXSAVE clear: best sse42.
  • AMX bits set: sapphirerapids 0 at XCR0 = 0xE7, normal at 0x600E7.
  • Patch file applies with git apply --check, forward and reverse.

Not run: full library build, repo tests, GCC/Clang xgetbv path, real Zen 5 hardware.

🤖 Generated with Claude Code

alanshurafa and others added 3 commits November 5, 2026 22:41
The CPU backend score checked CPUID feature bits only. On a machine
where CPUID advertises AVX-512 but the OS leaves the ZMM state off in
XCR0 (seen on Zen 5 Windows, XCR0 = 0x7), the cascadelake variant won
and the first 512-bit instruction raised an illegal-instruction fault.

Read XCR0 with xgetbv when OSXSAVE is set and score a variant 0 unless
the OS enables the state it needs: SSE+YMM for AVX-class variants,
opmask+ZMM for AVX-512, XTILECFG+XTILEDATA for AMX. Scores are
otherwise unchanged.

Fixes cjpais/Handy#2402.

Co-Authored-By: Claude Fable 5.1 <[email protected]>
ggml/ is regenerated by scripts/sync-ggml.sh from the upstream SHA plus
patches/ggml/*.patch; without a patch file the cpu-feats.cpp fix would
be dropped on the next sync.

Co-Authored-By: Claude Fable 5.1 <[email protected]>
macOS enables AVX-512 register state lazily, so XCR0 bits 5-7 are clear
until a thread first uses AVX-512. The XCR0 check therefore rejected the
AVX-512 variants on Intel Macs that support them. On Apple, take AVX-512
OS support from hw.optional.avx512f instead, as google/cpu_features does.

Also mark `is` unused for the x64 variant, which checks no CPUID bits and
otherwise warns under -Wextra. Patch 0004 regenerated to match.
@alanshurafa
alanshurafa marked this pull request as ready for review November 6, 2026 18:33
@alanshurafa
alanshurafa requested a review from cjpais as a code owner November 6, 2026 18:33
alanshurafa added a commit to alanshurafa/transcribe.cpp that referenced this pull request Nov 7, 2026

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Successfully merging this pull request may close these issues.

[BUG] Worker crashes with 0xC000001D: ggml picks the AVX-512 CPU backend while the OS does not enable AVX-512 state (XCR0=0x7)

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