CENG450_Project

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Name		Name	Last commit message	Last commit date
CPU		CPU
.gitignore		.gitignore
1test16_sq2.vhd		1test16_sq2.vhd
ALU.vhd		ALU.vhd
ALU_TB.vhd		ALU_TB.vhd
Adder.vhd		Adder.vhd
Barrel_Shift_Left.vhd		Barrel_Shift_Left.vhd
Barrel_Shift_Right.vhd		Barrel_Shift_Right.vhd
Branch.vhd		Branch.vhd
Branch_TB.vhd		Branch_TB.vhd
CPU.xise		CPU.xise
CPU_Pinout.ucf		CPU_Pinout.ucf
Clock_Prescaler.vhd		Clock_Prescaler.vhd
Controller.ucf		Controller.ucf
Controller.vhd		Controller.vhd
Controller_TB.vhd		Controller_TB.vhd
Decode.vhd		Decode.vhd
Decode_TB.vhd		Decode_TB.vhd
Decode_TB2.vhd		Decode_TB2.vhd
Display_Controller.vhd		Display_Controller.vhd
Execute.vhd		Execute.vhd
Execute_TB.vhd		Execute_TB.vhd
FORMAT_B_Test_Part1.vhd		FORMAT_B_Test_Part1.vhd
FORMAT_B_Test_Part2.vhd		FORMAT_B_Test_Part2.vhd
FORMAT_B_Test_Part3.vhd		FORMAT_B_Test_Part3.vhd
FORMAT_L_Test.vhd		FORMAT_L_Test.vhd
Fetch.vhd		Fetch.vhd
Fetch_TB.vhd		Fetch_TB.vhd
Final_Test.vhd		Final_Test.vhd
Instruction_Set_16bit_2016CorrectedLoadStoreFormat.pdf		Instruction_Set_16bit_2016CorrectedLoadStoreFormat.pdf
MUX.vhd		MUX.vhd
MUX2.vhd		MUX2.vhd
Memory.vhd		Memory.vhd
Official_RegFile_TB.vhd		Official_RegFile_TB.vhd
Pipeline.ucf		Pipeline.ucf
Pipeline.vhd		Pipeline.vhd
Pipeline_TB.vhd		Pipeline_TB.vhd
RAM.vhd		RAM.vhd
RAM_TB.vhd		RAM_TB.vhd
RAW_Handler.vhd		RAW_Handler.vhd
RAW_Handler_TB.vhd		RAW_Handler_TB.vhd
ROM.vhd		ROM.vhd
ROM_Real.vhd		ROM_Real.vhd
ROM_VHDL.vhd		ROM_VHDL.vhd
RegFile_ALU.xise		RegFile_ALU.xise
Register_File.vhd		Register_File.vhd
Register_File_TB.vhd		Register_File_TB.vhd
Shift_Right_TB.vhd		Shift_Right_TB.vhd
Simple_Controller.vhd		Simple_Controller.vhd
Simple_Controller_TB.vhd		Simple_Controller_TB.vhd
Writeback.vhd		Writeback.vhd
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