TestBench Code

`timescale 1ns/1ps

module tb_async_fifo_ecc;

    reg wr_clk;
    reg rd_clk;

    reg wr_rst_n;
    reg rd_rst_n;

    reg [7:0] s_data;
    reg s_valid;
    wire s_ready;

    wire [7:0] m_data;
    wire m_valid;
    reg m_ready;

    wire full;
    wire empty;

    wire ecc_corrected;
    wire ecc_error;


    // ========================================================
    // DUT
    // ========================================================

    async_fifo_ecc dut (
        .wr_clk(wr_clk),
        .wr_rst_n(wr_rst_n),

        .s_data(s_data),
        .s_valid(s_valid),
        .s_ready(s_ready),

        .rd_clk(rd_clk),
        .rd_rst_n(rd_rst_n),

        .m_data(m_data),
        .m_valid(m_valid),
        .m_ready(m_ready),

        .full(full),
        .empty(empty),

        .ecc_corrected(ecc_corrected),
        .ecc_error(ecc_error)
    );


    // ========================================================
    // Clocks
    // ========================================================

    initial begin
        wr_clk = 0;

        forever #5 wr_clk = ~wr_clk;
    end

    initial begin
        rd_clk = 0;

        forever #7 rd_clk = ~rd_clk;
    end


    // ========================================================
    // Reset
    // ========================================================

    initial begin

        wr_rst_n = 0;
        rd_rst_n = 0;

        s_data   = 0;
        s_valid  = 0;
        m_ready  = 0;

        #40;

        wr_rst_n = 1;
        rd_rst_n = 1;

        $display("========================================");
        $display("RESET RELEASED");
        $display("========================================");

    end


    // ========================================================
    // Write Task
    // ========================================================

    task write_data;
        input [7:0] data;

        begin

            @(posedge wr_clk);

            while (!s_ready)
                @(posedge wr_clk);

            s_data  <= data;
            s_valid <= 1'b1;

            @(posedge wr_clk);

            s_valid <= 1'b0;

            $display(
                "[WRITE] Time=%0t Data=%02h",
                $time,
                data
            );

        end

    endtask


    // ========================================================
    // Read Monitor
    // ========================================================

    always @(posedge rd_clk) begin

        if (m_valid && m_ready) begin

            $display(
                "[READ ] Time=%0t Data=%02h Corrected=%b Error=%b",
                $time,
                m_data,
                ecc_corrected,
                ecc_error
            );

        end

    end


    // ========================================================
    // Main Test
    // ========================================================

    integer i;

    initial begin

        wait(wr_rst_n && rd_rst_n);

        #20;

        // Enable output
        m_ready = 1'b1;

        // ----------------------------------------------------
        // Basic FIFO test
        // ----------------------------------------------------

        $display("");
        $display("========================================");
        $display("BASIC FIFO TEST");
        $display("========================================");

        for (i = 0; i < 10; i = i + 1) begin
            write_data(8'h10 + i);
        end


        // ----------------------------------------------------
        // Backpressure test
        // ----------------------------------------------------

        $display("");
        $display("========================================");
        $display("BACKPRESSURE TEST");
        $display("========================================");

        m_ready = 1'b0;

        #100;

        m_ready = 1'b1;


        // ----------------------------------------------------
        // More data
        // ----------------------------------------------------

        $display("");
        $display("========================================");
        $display("ADDITIONAL DATA TEST");
        $display("========================================");

        for (i = 0; i < 6; i = i + 1) begin
            write_data(8'hA0 + i);
        end


        #500;

        $display("");
        $display("========================================");
        $display("TEST COMPLETE");
        $display("========================================");

        $finish;

    end


    // ========================================================
    // ECC Fault Injection
    // ========================================================
    //
    // After some data has been written, deliberately flip
    // one bit in the FIFO memory.
    //
    // This demonstrates single-bit correction.
    // ========================================================

    initial begin

        wait(wr_rst_n && rd_rst_n);

        #120;

        $display("");
        $display("========================================");
        $display("ECC SINGLE-BIT FAULT INJECTION");
        $display("========================================");

        // Flip one encoded bit
        dut.mem[2][3] = ~dut.mem[2][3];

        $display(
            "Injected single-bit error into FIFO memory"
        );

    end


    // ========================================================
    // Waveform Dump
    // ========================================================

    initial begin

        $dumpfile("async_fifo_ecc.vcd");
        $dumpvars(0, tb_async_fifo_ecc);

    end

endmodule