I'm a computer engineering student at the University of Denver. I like the layer where hardware meets firmware: CPUs on FPGAs, small ASIC-flow designs, PCBs, and the protocols they speak. Right now I'm an avionics engineering intern, writing bare-metal C for flight hardware.
I graduate in June 2027 and I'm looking for full-time embedded, FPGA/RTL and avionics roles starting July 2027.
Portfolio: cshieldsce.github.io has a write-up for every project, with schematics, scope captures and layouts.
| Project | About |
|---|---|
| riscv-5i (repo) | 5-stage pipelined RV32I core in SystemVerilog. Passes all 482 RISCOF compliance tests, runs on a Zynq-7000, and went through a Sky130 layout. |
| smallcore (repo) | A tiny programmable protocol engine in Verilog, like a PIO block. UART, SPI, I2C, SWD and CAN from small programs, hardened through a real ASIC flow. |
| CANtap | CAN bus tooling: desktop app, CLI, and the firmware and board for an isolated CAN FD adapter, all on one Rust backend. Still in progress. |
| ECG amplifier | Op-amp front end that pulls a heartbeat out of three skin electrodes, with an LTspice model to match. |
| PSoC 6 PDM driver for Zephyr (repo) | Gets the PDM microphones on Infineon's CY8CKIT-062S2-AI working under Zephyr without ModusToolbox. |
| Arduino DSP shield | Two-layer KiCad shield with an IMU, OLED and a 10-bit R-2R DAC. |
There's more on the site: a weather balloon sensor shield, a 5-bit DAC drawn in Electric VLSI, Verilog labs on a DE10-Lite, a balancing robot board I debugged over SWD, and a pile of analog circuits that I simulated and then measured on a scope.