split critical edges during x86 register allocation by can-lehmann · Pull Request #87 · can-lehmann/metajit.cpp

can-lehmann · 2026-09-30T19:20:56Z

No description provided.

github-actions · 2026-09-30T19:23:24Z

Coverage

File	Lines	Functions	Regions	Branches
`genext.hpp`	🔴 59.44%	🟡 80.95%	🟡 79.65%	🟡 79.34%
`jitir.hpp`	🔴 54.28%	🔴 67.28%	🔴 58.61%	🔴 57.30%
`jitir_llvmapi.hpp`	🔴 54.86%	🟡 80.00%	🟢 98.21%	🔴 50.00%
`llvmgen.hpp`	🔴 66.38%	🟡 70.00%	🟡 85.81%	🟡 87.18%
`lowerllvm.hpp`	🔴 63.60%	🟡 75.00%	🔴 41.32%	🔴 56.49%
`x86gen.hpp`	🔴 63.54%	🟡 80.00%	🟡 77.18%	🟡 83.70%
`x86insts.inc.hpp`	-	-	-	-
TOTAL	🔴 57.01%	🟡 70.10%	🔴 67.15%	🔴 68.03%

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

jitir.hpp (100%)
x86gen.hpp (0.0%): Missing lines 1723-1724,1852-1865,1923-1926

Summary

Total: 23 lines
Missing: 20 lines
Coverage: 13%

x86gen.hpp

Lines 1719-1728

  1719         initial_state[info.fixed.id()] = vreg(arg);
  1720       }
  1721       _blocks[0]->set_regalloc(initial_state);
  1722 
! 1723       for (size_t block_index = 0; block_index < _blocks.size(); block_index++) {
! 1724         X86Block* block = _blocks[block_index];
  1725         if (block->regalloc()) {
  1726           load_state(reg_file, block->regalloc());
  1727         }

Lines 1848-1869

  1848 
  1849           if (std::holds_alternative<X86Block*>(inst->imm())) {
  1850             X86Block* target = std::get<X86Block*>(inst->imm());
  1851             if (target->regalloc()) {
! 1852               if (inst->kind() != X86Inst::Kind::Jmp) {
! 1853                 X86Block* edge = _builder.build_block();
! 1854                 edge->set_name(block->name());
! 1855                 Reg* state = (Reg*) _allocator.alloc(sizeof(Reg) * reg_file.size(), alignof(Reg));
! 1856                 for (size_t it = 0; it < reg_file.size(); it++) {
! 1857                   state[it] = reg_file[Reg::phys(it)];
! 1858                 }
! 1859                 edge->set_regalloc(state);
! 1860                 _builder.move_before(edge, nullptr);
! 1861                 _builder.jmp(target)->set_name(inst->name());
! 1862                 _blocks.insert(_blocks.begin() + block_index + 1, edge);
! 1863                 inst->set_imm(edge);
! 1864                 continue;
! 1865               }
  1866               // Restore regalloc state
  1867               if (target->name() < block->name()) {
  1868                 // Backedge
  1869                 assert(target->loop());

Lines 1919-1930

  1919           }
  1920         }
  1921       }
  1922 
! 1923       for (size_t it = 0; it < _blocks.size(); it++) {
! 1924         _blocks[it]->set_name(it);
! 1925       }
! 1926 
  1927       #ifdef METAJIT_DEBUG
  1928       for (X86Block* block : _blocks) {
  1929         if (block->regalloc()) {
  1930           _builder.move_to_begin(block);

github-actions · 2026-09-30T19:31:20Z

Coverage

File	Lines	Functions	Regions	Branches
`genext.hpp`	🔴 59.44%	🟡 80.95%	🟡 79.65%	🟡 79.34%
`jitir.hpp`	🔴 54.28%	🔴 67.28%	🔴 58.61%	🔴 57.30%
`jitir_llvmapi.hpp`	🔴 54.86%	🟡 80.00%	🟢 98.21%	🔴 50.00%
`llvmgen.hpp`	🔴 66.38%	🟡 70.00%	🟡 85.81%	🟡 87.18%
`lowerllvm.hpp`	🔴 63.60%	🟡 75.00%	🔴 41.32%	🔴 56.49%
`x86gen.hpp`	🔴 63.54%	🟡 80.00%	🟡 77.18%	🟡 83.70%
`x86insts.inc.hpp`	-	-	-	-
TOTAL	🔴 57.01%	🟡 70.10%	🔴 67.15%	🔴 68.03%

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

jitir.hpp (100%)
x86gen.hpp (0.0%): Missing lines 1723-1724,1852-1865,1923-1926

Summary

Total: 23 lines
Missing: 20 lines
Coverage: 13%

x86gen.hpp

Lines 1719-1728

  1719         initial_state[info.fixed.id()] = vreg(arg);
  1720       }
  1721       _blocks[0]->set_regalloc(initial_state);
  1722 
! 1723       for (size_t block_index = 0; block_index < _blocks.size(); block_index++) {
! 1724         X86Block* block = _blocks[block_index];
  1725         if (block->regalloc()) {
  1726           load_state(reg_file, block->regalloc());
  1727         }

Lines 1848-1869

  1848 
  1849           if (std::holds_alternative<X86Block*>(inst->imm())) {
  1850             X86Block* target = std::get<X86Block*>(inst->imm());
  1851             if (target->regalloc()) {
! 1852               if (inst->kind() != X86Inst::Kind::Jmp) {
! 1853                 X86Block* edge = _builder.build_block();
! 1854                 edge->set_name(block->name());
! 1855                 Reg* state = (Reg*) _allocator.alloc(sizeof(Reg) * reg_file.size(), alignof(Reg));
! 1856                 for (size_t it = 0; it < reg_file.size(); it++) {
! 1857                   state[it] = reg_file[Reg::phys(it)];
! 1858                 }
! 1859                 edge->set_regalloc(state);
! 1860                 _builder.move_before(edge, nullptr);
! 1861                 _builder.jmp(target)->set_name(inst->name());
! 1862                 _blocks.insert(_blocks.begin() + block_index + 1, edge);
! 1863                 inst->set_imm(edge);
! 1864                 continue;
! 1865               }
  1866               // Restore regalloc state
  1867               if (target->name() < block->name()) {
  1868                 // Backedge
  1869                 assert(target->loop());

Lines 1919-1930

  1919           }
  1920         }
  1921       }
  1922 
! 1923       for (size_t it = 0; it < _blocks.size(); it++) {
! 1924         _blocks[it]->set_name(it);
! 1925       }
! 1926 
  1927       #ifdef METAJIT_DEBUG
  1928       for (X86Block* block : _blocks) {
  1929         if (block->regalloc()) {
  1930           _builder.move_to_begin(block);

github-actions · 2026-09-30T19:33:45Z

Coverage

File	Lines	Functions	Regions	Branches
`genext.hpp`	🔴 59.44%	🟡 80.95%	🟡 79.65%	🟡 79.34%
`jitir.hpp`	🔴 54.28%	🔴 67.28%	🔴 58.61%	🔴 57.30%
`jitir_llvmapi.hpp`	🔴 54.86%	🟡 80.00%	🟢 98.21%	🔴 50.00%
`llvmgen.hpp`	🔴 66.38%	🟡 70.00%	🟡 85.81%	🟡 87.18%
`lowerllvm.hpp`	🔴 63.60%	🟡 75.00%	🔴 41.32%	🔴 56.49%
`x86gen.hpp`	🔴 63.54%	🟡 80.00%	🟡 77.18%	🟡 83.70%
`x86insts.inc.hpp`	-	-	-	-
TOTAL	🔴 57.01%	🟡 70.10%	🔴 67.15%	🔴 68.03%

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

jitir.hpp (100%)
x86gen.hpp (0.0%): Missing lines 1723-1724,1852-1865,1923-1926

Summary

Total: 23 lines
Missing: 20 lines
Coverage: 13%

x86gen.hpp

Lines 1719-1728

  1719         initial_state[info.fixed.id()] = vreg(arg);
  1720       }
  1721       _blocks[0]->set_regalloc(initial_state);
  1722 
! 1723       for (size_t block_index = 0; block_index < _blocks.size(); block_index++) {
! 1724         X86Block* block = _blocks[block_index];
  1725         if (block->regalloc()) {
  1726           load_state(reg_file, block->regalloc());
  1727         }

Lines 1848-1869

  1848 
  1849           if (std::holds_alternative<X86Block*>(inst->imm())) {
  1850             X86Block* target = std::get<X86Block*>(inst->imm());
  1851             if (target->regalloc()) {
! 1852               if (inst->kind() != X86Inst::Kind::Jmp) {
! 1853                 X86Block* edge = _builder.build_block();
! 1854                 edge->set_name(block->name());
! 1855                 Reg* state = (Reg*) _allocator.alloc(sizeof(Reg) * reg_file.size(), alignof(Reg));
! 1856                 for (size_t it = 0; it < reg_file.size(); it++) {
! 1857                   state[it] = reg_file[Reg::phys(it)];
! 1858                 }
! 1859                 edge->set_regalloc(state);
! 1860                 _builder.move_before(edge, nullptr);
! 1861                 _builder.jmp(target)->set_name(inst->name());
! 1862                 _blocks.insert(_blocks.begin() + block_index + 1, edge);
! 1863                 inst->set_imm(edge);
! 1864                 continue;
! 1865               }
  1866               // Restore regalloc state
  1867               if (target->name() < block->name()) {
  1868                 // Backedge
  1869                 assert(target->loop());

Lines 1919-1930

  1919           }
  1920         }
  1921       }
  1922 
! 1923       for (size_t it = 0; it < _blocks.size(); it++) {
! 1924         _blocks[it]->set_name(it);
! 1925       }
! 1926 
  1927       #ifdef METAJIT_DEBUG
  1928       for (X86Block* block : _blocks) {
  1929         if (block->regalloc()) {
  1930           _builder.move_to_begin(block);

github-actions · 2026-09-30T19:38:03Z

Coverage

File	Lines	Functions	Regions	Branches
`genext.hpp`	🔴 59.44%	🟡 80.95%	🟡 79.65%	🟡 79.34%
`jitir.hpp`	🔴 54.38%	🔴 67.28%	🔴 58.80%	🔴 57.51%
`jitir_llvmapi.hpp`	🔴 54.86%	🟡 80.00%	🟢 98.21%	🔴 50.00%
`llvmgen.hpp`	🔴 66.38%	🟡 70.00%	🟡 85.81%	🟡 87.18%
`lowerllvm.hpp`	🔴 63.60%	🟡 75.00%	🔴 41.32%	🔴 56.49%
`x86gen.hpp`	🔴 63.54%	🟡 80.00%	🟡 77.18%	🟡 83.70%
`x86insts.inc.hpp`	-	-	-	-
TOTAL	🔴 57.07%	🟡 70.10%	🔴 67.25%	🔴 68.15%

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

jitir.hpp (100%)
x86gen.hpp (0.0%): Missing lines 1723-1724,1852-1865,1923-1926

Summary

Total: 23 lines
Missing: 20 lines
Coverage: 13%

x86gen.hpp

Lines 1719-1728

  1719         initial_state[info.fixed.id()] = vreg(arg);
  1720       }
  1721       _blocks[0]->set_regalloc(initial_state);
  1722 
! 1723       for (size_t block_index = 0; block_index < _blocks.size(); block_index++) {
! 1724         X86Block* block = _blocks[block_index];
  1725         if (block->regalloc()) {
  1726           load_state(reg_file, block->regalloc());
  1727         }

Lines 1848-1869

  1848 
  1849           if (std::holds_alternative<X86Block*>(inst->imm())) {
  1850             X86Block* target = std::get<X86Block*>(inst->imm());
  1851             if (target->regalloc()) {
! 1852               if (inst->kind() != X86Inst::Kind::Jmp) {
! 1853                 X86Block* edge = _builder.build_block();
! 1854                 edge->set_name(block->name());
! 1855                 Reg* state = (Reg*) _allocator.alloc(sizeof(Reg) * reg_file.size(), alignof(Reg));
! 1856                 for (size_t it = 0; it < reg_file.size(); it++) {
! 1857                   state[it] = reg_file[Reg::phys(it)];
! 1858                 }
! 1859                 edge->set_regalloc(state);
! 1860                 _builder.move_before(edge, nullptr);
! 1861                 _builder.jmp(target)->set_name(inst->name());
! 1862                 _blocks.insert(_blocks.begin() + block_index + 1, edge);
! 1863                 inst->set_imm(edge);
! 1864                 continue;
! 1865               }
  1866               // Restore regalloc state
  1867               if (target->name() < block->name()) {
  1868                 // Backedge
  1869                 assert(target->loop());

Lines 1919-1930

  1919           }
  1920         }
  1921       }
  1922 
! 1923       for (size_t it = 0; it < _blocks.size(); it++) {
! 1924         _blocks[it]->set_name(it);
! 1925       }
! 1926 
  1927       #ifdef METAJIT_DEBUG
  1928       for (X86Block* block : _blocks) {
  1929         if (block->regalloc()) {
  1930           _builder.move_to_begin(block);

can-lehmann added 2 commits September 30, 2026 21:06

Split critical edges during x86 register allocation

c4516bd

Avoid dominance checks for unvisited successors

bda6c3c

Document branch naming convention

5425670

Proofread repository instructions

4021036

Document remaining project files

dce63aa

can-lehmann merged commit 12a5e38 into main Sep 30, 2026
2 checks passed

Navigation Menu

split critical edges during x86 register allocation - #87

split critical edges during x86 register allocation#87
can-lehmann merged 5 commits into
mainfrom
can-critical-edge-splitting

can-lehmann commented Sep 30, 2026

Uh oh!

github-actions Bot commented Sep 30, 2026

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

github-actions Bot commented Sep 30, 2026

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

github-actions Bot commented Sep 30, 2026

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

Uh oh!

github-actions Bot commented Sep 30, 2026

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

1 participant

Conversation

can-lehmann commented Sep 30, 2026

Uh oh!

github-actions Bot commented Sep 30, 2026

Coverage

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

github-actions Bot commented Sep 30, 2026

Coverage

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

github-actions Bot commented Sep 30, 2026

Coverage

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

Uh oh!

github-actions Bot commented Sep 30, 2026

Coverage

Diff Coverage

Diff: origin/main...HEAD, staged and unstaged changes

Summary

x86gen.hpp

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

1 participant