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gemm_ex: general GEMM domain + fp8 fallback for refused shapes (replaces #139) - #214
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One commit with the tree of CUDApp#139 head 117d8d7 on main e7cc7d6. It replaces #139 so that the build-pic/ objects added in 446f84c and removed in 117d8d7 (151 files, 5,797,971 bytes) never enter main history under a merge commit. Collected #139 commits: - 117d8d7 Remove build-pic/ objects committed by mistake in 446f84c (author: aien-spark) - 446f84c gemm_ex: chip receipt on the merged kernels (902 checks, evidence/GEMM-GENERAL-00c9cf9); README points at it (author: aien-spark) - 4e6609f gemm_ex after main merge: link gemm_ex into the native runtime test; drift baseline records omega's bw_warp_sim_tc.h blob (author: aien-spark) - fc591d6 gemm_ex test: DnnGpu's adversarial bf16 K=1808 regression (got exactly 0x1p+0, err above the old flat bound, inside the step_c() bound) (author: Drake Stapleton) - 7c1a708 gemm_ex ab-2: the remaining small-cell overhead is measured, not yet attributed (author: Drake Stapleton) - 02cd03d gemm_ex A/B ab-2 receipt: 0/18 REGRESSION, r 0.94-1.24 (ab-1 2.17-3.25), plan gate FAIL in 5 small cells; chip tier PASS 901 at 0d2b14a; overhead recorded in API.md 9.8 (author: Drake Stapleton) - df0e1ca gemm_ex A/B ab-2: predeclared plan (before any ab-2 timed run; ab-1 stands) (author: Drake Stapleton) - 0d2b14a gemm_ex: host overhead (ab-1 gate FAIL): vector inf/NaN scan, lazy buffers, one-part path without the double sum, C3 writes C in place for the bit-for-bit case (author: Drake Stapleton) - 30dee06 gemm_ex A/B ab-1 receipt: 18/18 cells REGRESSION (r 2.17-3.25), plan gate FAIL (author: Drake Stapleton) - 1da99c1 gemm_ex served-shape A/B: predeclared plan, driver and hold script (before any timed run) (author: Drake Stapleton) - 90c3f89 gemm_ex: runtime API 0.6.0 manifest entries, API.md section 9.8, README limits, successor #144 (author: Drake Stapleton) - eb5b892 gemm_ex test: comment order (author: Drake Stapleton) - e398f0b gemm_ex test: per-step bound constant from the chip-exact model, compounding (author: Drake Stapleton) - 34f1b31 manifest: OmegaGpuFp8GemmInfo 88 bytes (+general), OmegaGpuFp8Info.general field, omega_gpu_fp8_general_rows internal (make test-runtime-api PASS) (author: Drake Stapleton) - b28372d evidence: GEMM-GENERAL-fba0384 chip receipts (gemm_ex 901 checks PASS; regression gemm/fp8/fp8gemm/matmul; part0of4 = first run whose one FAIL was a test defect: mutant 5 on a one-k-block shape) (author: Drake Stapleton) - fba0384 gemm_ex: general GEMM entry (any M,N,K, op N/T, ld, alpha/beta, strided batch, bf16/f16/f32-via-bf16x3/fp8 scales) + fp8 GEMV/grouped GEMM fallback for refused shapes (author: Drake Stapleton) - 00c9cf9 Merge remote-tracking branch 'origin/main' into pr139 (merge, author: aien-spark) - 8931aff Merge remote-tracking branch 'origin/main' into pr139 (merge, author: aien-spark)
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## Recovered host-only Ampere port Final source: `3b6ca6fda726a6b2eb01100ae155fbcb890d00af`. Draft, not merged or deployed. Recovery found the `__truncsfhf2` source repair already complete at `592cee255eaba4b86c5a823ed071c2773a3d4f13`; it did not replace that Omega implementation with libgcc. This follow-on fixes CodeQL62 in the offline cubin fixture writer by creating new files with mode0600, closes the descriptor if fdopen fails, and reconciles the documentation's stale acceptance inventory. Existing file permissions are intentionally unchanged; this is a new-file creation repair, not a broader overwrite/symlink policy change. ## Dependencies and production boundary - Exact omega-bridge36 source: `ead98302ff0a649c49c3f2c7568af5e1b3da33eb`, pinned by `om/omega-bridge.lock`. All40 roots:37 bounded hosted compositions and import-free revision/epoch/f16 scalar units. No executable-code trampoline. - Binary32-to-binary16 RNE implementation is `om/numeric/f16.om`, emitted through bridge-freest; the C caller bitcasts and uses its checked scalar ABI. The hosted `_Float16` cast is a verification oracle only. Production scalar object has no undefined symbols; no `__truncsfhf2` or libgcc production dependency was added. - Compiler `2c82480596bbdc50cda9626866209ef662d5834f278f839ff4ce0250c495029f` at omega-mv `e5b32567a7aff3ce594e3254a622a846a6cd190b`; baseline `191b776ef98821597c3e30655da6d680a9b66edbc9ceaca3c39c61ea6df098e9` remains required. Converter/frontend hashes are checked before installation. All5 independently corrupted-pin controls refused exit3 with zero installed outputs. - Bridge36 behavior CI40758894095 remains PASS at its exact source. Native x86 Omega compiler923 and bridge37 are separate, not prerequisites. Guide114 is separately owned; no guide source or pin was changed by this recovery. ## Final host behavior and controls Clean detached source3b6ca6fd, native AArch64 host: `OMEGA_SEED=<191b baseline> OMEGA_OMC=<2c824 seeded compiler> OMEGA_MV=<e5b32567 tree> OMEGA_BRIDGE=<ead98302 tree> OMEGA_BRIDGE_DIR=<ead98302 tree> make -j2 all test test-native-artifact zero-cuda-gate ampere-device-build test-ampere-cubin-disasm` Exit0; `CUDA++ HOST TESTS PASS (58 targets)`. Byte-identical40-root regeneration; F16 boundaries/native stepped sweep/six mutant controls; unchanged freestanding import allowlist and canary refusal; Ampere cubin/numeric, simulated RM/session ordering/VRAM/target refusals; native artifacts, zero-CUDA probe rejection and offline cubin decoding passed. Device-build is build-only, not device execution. Fixture security controls: fresh output under umask000 is0600; historical592cee writer produces0666 with identical cubin bytes and fails the private-creation check; preexisting0666 output stays0666 with identical bytes; nonexistent-parent output refuses exit1 without creating files; no-output invocation succeeds without creating a fixture. Current-head CodeQL check123126643103 SUCCESS: no new alerts in code changed by this pull request. An initial attempt in the recovered x86pre tree failed because preexisting x86 `build/test_ampere_runtime` was reused by a hardcoded build/ target despite OUT_DIR; on ARM its dynamic loader was absent. Those artifacts were preserved. The clean detached final tree above passed; the contaminated attempt is not reported as PASS. ## Native x86 consumer acceptance Current-head native x86 workflow40776306246 **SUCCESS**, completed2026-10-28T22:33:33Z: https://github.com/aien-dev/CUDApp/actions/runs/40776306246. Candidate source `3b6ca6fda726a6b2eb01100ae155fbcb890d00af`; actual checked-out PR merge `cf65a61c8b95f7d0d7b51c5618a9dc87bcbb8cf4` onto base `c6977b4906229fe83f41103b7eff65b64a0986d6`. Both provenance-baseline and native-x86-host jobs passed. Three consumer ELF headers are x86-64;58 host targets,40-root regeneration, F16 boundary/sweep/mutant controls, native artifacts and zero-CUDA passed. The unchanged17-file freestanding link exposes only memcmp/memcpy/memset/strcmp/strlen, not a half-conversion helper. Final offline oracle:2169 kernels, every opcode/operand matched, mutated operand refused;73 native-FP8 kernels refused. Compiler/converter QEMU execution remains EMULATED provenance; the x86 compiled-C consumers actually ran natively. Handler teardown passed. Physical RTX qualification remains NOT_RUN. Prior source592cee run40762515409 SUCCESS checked out PR merge `6a2b759333ce791663d0107949659c7a3cd887bb`: three x86-64 ELF headers,58 host targets,40-root regeneration and2169-kernel exact SM86 offline oracle. Current-head outcome is not inferred from that earlier run. AArch64 compiler/converter execution under pinned QEMU is EMULATED provenance; compiled-C x86 consumers are NATIVE. Neither establishes a native x86 Omega compiler result. ## Scope and physical NOT_RUN Separate SM121 MMIO work remains separate; this recovery did not touch176/173/174/175, bridge37 or CodexIntegration. No gate was weakened and historical receipts remain unchanged. RTX3090 and RTX3060Ti execution, loader acceptance, BAR/coherence, full device numerical math and safe VRAM-refusal device proof remain NOT_RUN. They require the actual card host, pinned580.173.02 open module, unambiguous PCI BDF and current explicit GPU authorization. Follow tests/ampere/README.md and doctor/run.py; cached mappings refuse. Host simulation and offline disassembly are not physical qualification. No GPU, driver, host binfmt configuration or live production service was touched. ## Independent review (Main desk, 2026-10-31) Adversarial review by Cudapp170b and C170c (agent lanes), plus a read-only second-agent review by Rev1001. Rev1001 gave **NO_WEAKENING** on efaf8d7. It also gave NO_WEAKENING on the final diff 570b5d6 (fixes for its notes a and b, plus the loop-scan follow-up). Decisions taken while merging main: - Binding cutover: the hosted encoder goes through portable `src/cudapp_om_bw_enc_sm121.c`. - The API is now 0.9.0, not 0.8.0. Main #214 already used 0.8.0, so the manifest, header and API.md lines 3, 39, 41 and 648 were bumped. - Drift control 3 skips any numeric path absent from OMEGA_REF, with a message. All four paths are present in the real omega-mv, so the control still runs there and stays red on all four. - Dropped: the `CUDAPP_MEMINFO` env override, replaced by main's CodeQL #40 `test_set_meminfo` hook. - efaf8d7 decodes each distinct kernel once, concurrently, in the oracle (`tools/ampere_nvdisasm.py`, 3131 distinct of 4679). It passed locally in 3m00s; a planted operand flip gives rc1 and names the file. Fixes from Rev1001's review (commit 570b5d6): - (b) Uniform destination rule. The encoder writes a uniform register only for LDCU/LDCU64; on IMAD/ISETP, `is_uniform` marks a uniform source. Three places still read any `is_uniform` dst as uniform, and now all three use the encoder's predicate: - `omega_bw_ir_append`, the allocator's live intervals; - `check_loop_invariant` in `omega_gpu_attention_api.c`; - `check_loop_invariant` in `omega_gpu_elementwise_api.c`. Regression test `test_uniform_source_dst` (tests/bw_hazard_test.c) builds a uniform-source IMAD whose GPR destination is read later. - On efaf8d7 source: `bw_hazard_test: 264 checks, 3 failed: FAIL`. - The dst interval starts at IR 4, not 2. - The dst reuses R2, the GPR of a value still live at IR 3. - The uniform interval of the same index is polluted, with first def 2 instead of 5. - With the fix: `264 checks, 0 failed: PASS`. - Apart from those lines, the sweep output is identical before and after (2360 distinct kernels, 189 findings). Only LDCU64 builders set `is_uniform` in src/, so production kernels are unchanged. - (a) `tools/test_bw_spec_encoder.sh`: a skipped AArch64 native probe now exits 3 (NOT_RUN, the script's existing code) instead of 0, unless `BW_SPEC_NATIVE_PROBE_NOT_RUN_OK=1`. `make test-om-spec-encoder` sets that variable only on non-AArch64 hosts, and the log then names the accepted NOT_RUN row. Exercised runs: - AArch64: full probe, rc 0. - Fake x86 CC, no acknowledgement: rc 3. - Fake x86 CC with acknowledgement: rc 0, NOT_RUN line printed. Local checks (AArch64, cores 6-9,15-19 at nice 19): - On 570b5d6: `make -j2 test` rc 0, `CUDA++ HOST TESTS PASS (74 targets)`; spec encoder full PASS; `crumb verify` OK, 35 crumbs. - After merging main 105d65d (head 19d7dc8): `tests/gates/cudapp-run.sh runtime-api` rc 0, with both RESULT: PASS lines and every negative control caught; `make test-runtime-api-semver` PASS (0.8.0 -> 0.9.0); crumb verify OK. Trailer disclosure: this PR has 9 `Signed-off-by: Drake Stapleton <[email protected]>` trailers, on commits a80179b, 8cce4a6, 2e6bf8c, b026505, 1147b0c, fd9f23b, ae65cd6, 83c2a8a and dbb1b50. Their author and committer are the Drake identity, which was not verified. [INFERENCE] The AmperePort agent lane wrote them. The PR merges with a merge commit, so the trailers stay as written. NOT_RUN: - GB10 silicon for the sm_121 encoder/allocator uniform-destination change. Production bytes are expected to be unchanged, but that is not chip evidence. The command is queued as item G in the batched window queue: `make hello-gpu && ./build/gpu_elementwise_test --out ... && ./build/gpu_attention_test --out ...`. - RTX3090/3060Ti device execution, as above. - The native AArch64 function-byte probe on x86 CI, which is reported as NOT_RUN. **Drift fix (99ec266):** CI drift went red against omega 2638a49b because `tests/bw_hazard_test.c` (a byte copy of omega 6d7b8838, no baseline row) now carries the sm_86 cases. Added baseline row = omega blob e052b09 plus comment; self-test PASS, a scratch omega edit to the file still FAILs. Rev1001 NO_WEAKENING. Note: commit 99ec266 carries author identity "x <x>" (pushed; not rewritten, no force-push).
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Replaces #139. Same tree as #139 head 117d8d7 (
git diff 117d8d71 f95dca37is empty), squashed into one commit on main e7cc7d6. Reason: #139 commit 446f84c added 151build-pic/objects (5,797,971 bytes) that 117d8d7 removed; a merge-commit merge would have kept those blobs in main history. No commit here touchesbuild-pic/. The commit message lists the 18 collected #139 commits with their authors.omega_gpu_gemm_ex: one entry with the cblas RowMajor shape contract (any M,N,K, op N/T, ld, alpha/beta, strided batch, f32 via bf16x3, bf16/f16/e4m3/e5m2, tensor or block fp8 scales), plus fp8 GEMV / grouped-GEMM fallback for refused shapes. Migration-pending C behindCUDAPP_MIGRATION_PENDING_GEMM_EX; .om successor #144.Original head 7c1a708; final #139 head 117d8d7.
Done
OmegaGpuFp8GemmInfo80 -> 88 bytes.make test-runtime-apiPASS (296 functions, 46 structs, 443 fields, 229 constants; 183 INTERNAL); semver check MINOR.evidence/GEMM-GENERAL-AB-20261027/ab-2/chip/).evidence/GEMM-GENERAL-AB-20261027/:NOT_RUN
make -k testpassed on 34f1b31 (CUDA++ HOST TESTS PASS, 48 targets, EXIT 0). It has not run on the PR head; only the gemm_ex host/sim tiers and the runtime-API check ran there.Independent review (Main desk, 2026-10-31)
Measured by the CudaChain lane on #139 head 117d8d7 (tree identical to this PR's head):
crumb verifyOK (33);make test-gpu-native-runtime27 pass (host, EXERCISED).build/gpu_gemm_ex_test->gemm_ex chip: PASS (902 checks). Evidence:evidence/GEMM-GENERAL-00c9cf9/.runtime_api_checkFAIL. Both controls strict.omega_gpu_gemm_ld, not a regression for existing callers (API.md 9.8).NOT_RUN: attribution of the small-cell overhead; full
make -k teston the head; served end-to-end timing; hardware qualification beyond the chip tier above.