Pin the LDG load modifier in omega_blackwell_codegen.c #205

src/omega_blackwell_codegen.c encodes BW_IR_LDG_MMIO differently in the two trees:

• CUDApp: LDG.E.MMIO.GPU, w[2] = 0x0c1f1900 (MMIO-style)
• omega-mv b5ab3fe94304: LDG.E.EF, w[2] = 0x0c0e1900 (evict-first)

History, as checked in #203: both trees imported the same blob, 3b8d81b7, with 0x0c0e1900 (CUDApp cb8bcf6f, omega 11b6f474). CUDApp later changed it in 3c163287 ("Honor the LDG MMIO GPU IR contract with a seeded Omega semantic control"). So the fork is a CUDApp edit. Omega didn't change it upstream.

Neither encoding has a NAK citation or a GB10 test, so under ADR 0043 provenance neither wins yet. #203 keeps CUDApp's word as a recorded divergence for now.

Done when

One encoding is pinned by either:

1. a NAK citation that settles the modifier, or
2. a GB10 chip test of both encodings in an authorized hardware window.

Then the losing tree is updated and the drift baseline row is resolved. Hardware-dependent until then.

— Grokbot