[TILELAB T2] Native .om tile GEMM and streaming softmax on GB10 with evidence #153

Parent: aien-dev/aien-architecture-mv#347. Implement the native Omega tile algorithm, without incorporating TileLang code or using its libraries/compiler/runtime. Consume Omega #906 (tile/layout and streaming-summary oracle) and the existing C1 #885 GPU validation boundary.

Existing code

• CUDApp #143 merged seeded .om SM121 encoder+cubin packer.
• CUDApp #146 merged GEMM optimizations; #145 general attention.
• Existing src/omega_gpu_session.c, src/omega_gpu_gemm.c, src/omega_gpu_platform_linux.c remain transitional C; no new C product path.
• GPU hardware uses NVIDIA open kernel module and signed GSP firmware unchanged.

Work / test

1. Pin exact compiler, Omega/IR/checker, CUDApp and hardware revisions. Run authored .om tile GEMM 16x16x16 and 1x32 softmax using the existing GB10 toolchain, without duplicating register allocator, command-list owner or runtime. Prefer validated Omegese GPU C1 path over hand-assembled bypass.
2. Verify chip numerical output with external independent oracle, deterministic reduction tree and sensible BF16/f16/F32 error budgets. For streaming attention, use correct global log-sum-exp merge across tiles; never normalize each tile independently and call it a row softmax.
3. Try small tile candidates (16x16,32x32,64x64,64x128/128x64 only if they fit actual resource constraints) and record staging, register use, resident memory, global vs L2/DRAM traffic if observable, kernel time and launch time. No theoretical speedup claimed as hardware evidence.
4. Red controls for corrupt kernel bits, invalid stride/layout/shape/dtype, missing checker/source hashes, resource overflow, unwritten output, forbidden code object, interrupted submission. Abort/report real failure, never print PASS on setup error.
5. Provide one host/GB10 test driver or extension to existing test targets with pinned source/binary identity and receipt verifier. A clean host can run T1 and report chip NOT_RUN if GPU reserved.

Safety and gates

Preserve resident 35B, chip leases and /tmp/aien-gb10.lock; device tests require approved free window. No firmware flash, signature bypass, driver/kernel change, reboot or serving deployment. Respect proposed GPU ADR #343 gates: no broad P2–P4 backend rewrite through this experiment. Mark IMPLEMENTED / EXERCISED_HOST / EXERCISED_GB10 / QUALIFIED precisely.

Acceptance

One actual physical GB10 GEMM and one complete-row softmax/streaming reduction result match independently checked values, all red controls caught, raw logs and exact SHA receipts retained. Comparisons with existing CUDApp baseline belong to GPU Head-to-Head #2.