Xilinx/Vitis-Tutorials#112
The ref_design <https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT/ref_files/design1>_ for this example provides not only the source code for applications, but also a Makefile to run
through the design generation process. To generate the binaries, run the following command:
Immediate-term Solution: Push a copy of docs (check docs-jp & docs-cn with @mkmatsui ) from the 2022.2 branch to the master branch.
Near-term solution: @RebeccaOHagan & @dasmohana will FAR links that have /tree/master/ to use /tree/version/ instead.
Longer-term solution: Maybe create a package or a release?
Xilinx/Vitis-Tutorials#112
Immediate-term Solution: Push a copy of
docs(checkdocs-jp&docs-cnwith @mkmatsui ) from the 2022.2 branch to the master branch.Near-term solution: @RebeccaOHagan & @dasmohana will FAR links that have
/tree/master/to use/tree/version/instead.Longer-term solution: Maybe create a package or a release?