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usb: ehci/ohci/uhci/xhci: fix root-port reset, power, and recovery - #107
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FengHeting merged 1 commit intoOct 20, 2026
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Four root-port problems found while reviewing the legacy HCD interrupt work: - EHCI's PORTSC definitions did not match the spec. PED was decoded as bit 1 (CSC), CSC/PEC as bits 17/18 (PTC), and PTC as bit 3, so the driver could not see the connect or error changes it was waiting for. The reset sequence also wrote the read-back value back unchanged, which cleared unrelated RW1C bits and asserted Reset with PED still set. Use the spec positions (PED 2, CSC 1, PEC 3, OCC 5, PTC 16), mask the change bits out of every reset/handoff write, and clear PED when asserting Reset as required. - Root-port power was never enabled where the controller leaves it to software. EHCI needs PP set after CONFIGFLAG; OHCI needs LPSC for ganged power or per-port PPS selected by PPCM, then the POTPGT delay; xHCI needs PP set before its first connect scan, since a port with PP=0 never reports CCS. UHCI has no port-power bit. QEMU hides all of this (EHCI PPC=0, OHCI NPS=1, xHCI PP=1). - A port that the controller disables while the device stays connected raises PEC/PESC without CSC. The workers acknowledged the change, kept the stale device object, and left the port disabled until a physical replug. Treat "enable changed to 0 while CCS is still set" as a reconnect and run the normal enumeration path. EHCI and xHCI keep failed_ports for failed attempts; the reset routines clear the change bits they raise, so a successful enumeration does not re-trigger this path. Build-tested with all four controllers enabled. The power and port-error paths are not reachable in QEMU, so runtime coverage needs real hardware. Signed-off-by: MicroFish <[email protected]> Co-Authored-By: Claude Code <[email protected]>
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Four root-port problems found while reviewing the legacy HCD interrupt work:
EHCI's PORTSC definitions did not match the spec. PED was decoded as bit 1 (CSC), CSC/PEC as bits 17/18 (PTC), and PTC as bit 3, so the driver could not see the connect or error changes it was waiting for. The reset sequence also wrote the read-back value back unchanged, which cleared unrelated RW1C bits and asserted Reset with PED still set. Use the spec positions (PED 2, CSC 1, PEC 3, OCC 5, PTC 16), mask the change bits out of every reset/handoff write, and clear PED when asserting Reset as required.
Root-port power was never enabled where the controller leaves it to software. EHCI needs PP set after CONFIGFLAG; OHCI needs LPSC for ganged power or per-port PPS selected by PPCM, then the POTPGT delay; xHCI needs PP set before its first connect scan, since a port with PP=0 never reports CCS. UHCI has no port-power bit. QEMU hides all of this (EHCI PPC=0, OHCI NPS=1, xHCI PP=1).
A port that the controller disables while the device stays connected raises PEC/PESC without CSC. The workers acknowledged the change, kept the stale device object, and left the port disabled until a physical replug. Treat "enable changed to 0 while CCS is still set" as a reconnect and run the normal enumeration path. EHCI and xHCI keep failed_ports for failed attempts; the reset routines clear the change bits they raise, so a successful enumeration does not re-trigger this path.
Build-tested with all four controllers enabled. The power and port-error paths are not reachable in QEMU, so runtime coverage needs real hardware.