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1. Prolepsis-soc Prolepsis-soc Public

   Prolepsis: An ISA-agnostic, RTL-based predictive Thermal Management Unit (TMU) for multicore processors, featuring Kalman-filter temperature forecasting.

   Verilog 1

2. MobileNet-Accelerator-RTL MobileNet-Accelerator-RTL Public

   🏆 Top 100 submission for the DVCon India 2026 Design Contest. A highly optimized, Verilog-based MobileNet Accelerator featuring a custom Systolic Array and on-the-fly Global Average Pooling.

   Verilog

3. AES128-LowPower-Architecture AES128-LowPower-Architecture Public template

   Forked from tr0san/AES128bit

   Low-power AES-128 hardware architecture in Verilog, achieving a 50% reduction in dynamic power through parallel duplication and architecture-driven voltage scaling.

   Verilog

4. rtl-riscv32 rtl-riscv32 Public

   A 32-bit RISC-V (RV32I) processor implemented in Verilog using a single-cycle architecture. Includes instruction fetch, decode, ALU execution, register file operations, and basic control logic for …

   Verilog

5. algorithmic-fairness-analysis algorithmic-fairness-analysis Public

   Quantifying and mitigating educational bias in gig economy routing algorithms using causal models and constrained optimization.

   Python

6. CMOS-Standard-Cell-Library CMOS-Standard-Cell-Library Public

   CMOS Standard Cell Library & 1-Bit Full Adder: A bottom-up digital design project using LTspice. Features transistor-level implementation of primitives (NAND/NOR/XOR) and hierarchical design of a 1…

   Prolog 1