Name		Name	Last commit message	Last commit date
lab1_tcl/tb		lab1_tcl/tb
lab2_entities		lab2_entities
lab3_DSP		lab3_DSP
lab4_bram_dp_simple_be		lab4_bram_dp_simple_be
lab5_pipelines_and_systolic_arrays		lab5_pipelines_and_systolic_arrays
lab8_APB_and_CRC		lab8_APB_and_CRC
lab9_gcc_make		lab9_gcc_make
.gitignore		.gitignore
README.md		README.md

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FPGA-practicum

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learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

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