Skip to content
View RajMandaliya's full-sized avatar
  • Los Angeles, USA

Block or report RajMandaliya

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
RajMandaliya/README.md

Hey, I'm Raj πŸ‘‹

Software Engineer working on low-level systems, high-performance infrastructure, and things that have to be fast and correct at the same time.

I build systems from the ground up β€” a 16-bit CPU with a working pipeline and cache, an electronic exchange that replays real NASDAQ market data through an FPGA-style matching engine, Rust edge services handling 10M+ requests daily, and event-driven fintech pipelines. Currently contributing to NVIDIA's infra-controller (NICo), an open-source bare-metal/DPU lifecycle management system.

  • βš™οΈ Computer architecture β€” ISA design, pipeline hazards, cache modeling, FPGA-style dataflow
  • πŸ¦€ High-performance systems in Rust (Tokio, Actix Web, lock-free data structures)
  • πŸ“ˆ Market data and exchange internals β€” binary protocols, order books, latency measurement
  • πŸ“‘ Event-driven architecture with Apache Kafka at production scale
  • ☁️ Cloud-native infrastructure β€” Docker, Kubernetes, AWS

πŸ”§ Open Source Contributions

NVIDIA infra-controller (NICo)

A large-scale Rust systems codebase for bare-metal and DPU lifecycle management. Contributing by navigating unfamiliar production code, root-causing issues with real evidence rather than assumptions, and working directly with the maintainer team.

  • Diagnosed and closed a test-coverage gap in the mock BMC test harness β€” one hardware type had no way to be tested as a host machine at all. Added the missing test infrastructure and a regression test. (Merged)
  • Found and filed a MachineId-collision bug affecting four hardware mock types, backed by reproducible test evidence; confirmed and fixed by a project maintainer.
  • Traced a reported regression to its exact root cause by reproducing the failure against a real local cloud-init installation (not just reading documentation), and proposed a fix currently under maintainer review.

Stack: Rust Β· Tokio Β· PostgreSQL Β· Kubernetes Β· gRPC


πŸš€ Featured Projects

πŸ“ˆ tickpipe β€” Hardware-Accurate Electronic Exchange

A C++20 exchange that replays a full day of real NASDAQ TotalView-ITCH 5.0 market data β€” 8.7 GB, 282 million messages β€” and reconstructs the order book message by message.

  • Complete ITCH 5.0 decoder covering all 21 message types with per-type length validation; zero malformed messages across 282,229,684 parsed
  • Order-reference resolution layer β€” five of the eight book-affecting ITCH messages carry only an order ID, so the receiver has to remember every resting order. Fixed-capacity open-addressing table, zero allocation during replay
  • Matching engine modeled as a 5-stage FPGA pipeline: price-indexed ladder (slot = (price βˆ’ base) / tick) instead of a searched table, best bid/ask via a priority encode over an occupancy bitmap, no heap on the hot path
  • 2Γ— faster than the STL control implementation with a tighter tail β€” 40 ns vs 82 ns mean, 55 ns vs 162 ns at p99. Batch-mean methodology, since the platform clock only resolves 100 ns
  • Reproducible FNV-1a digests over every book operation and the full ladder β€” the same input file yields identical hashes on any machine, compiler or optimization level
  • Reconstructed AAPL's book to a 4-cent spread at the closing bell, and independently recovered the after-hours earnings print

Stack: C++20 Β· NASDAQ ITCH 5.0 Β· Lock-free / allocation-free design Β· CMake Β· Ninja


πŸ–₯️ cpu16 β€” Custom 16-bit CPU Emulator

A complete CPU built from first principles in Rust. Every design decision β€” instruction encoding, memory layout, interrupt handling β€” made deliberately and documented.

  • Custom 35-instruction ISA with 16-bit fixed-width encoding and 5-bit FLAGS register
  • Two-pass assembler with forward-reference resolution compiling .asm β†’ binary
  • 5-stage in-order pipeline (IF β†’ ID β†’ EX β†’ MEM β†’ WB) with RAW data hazard stall detection, flag hazard detection for conditional branches, and 2-cycle branch flush
  • Direct-mapped write-through L1 cache classifying misses as cold vs conflict; demonstrates cache thrashing on bubble sort's non-sequential access pattern
  • 6 assembly programs: bubble sort, binary search, Sieve of Eratosthenes, RPN stack calculator, Fibonacci, Factorial
  • 49 integration tests Β· 5 versioned releases Β· CI: fmt + clippy + test on every push

Stack: Rust Β· Custom ISA Β· Pipeline Simulation Β· Cache Modeling Β· Systems Programming


πŸ¦€ Mini-Agent: Rust AI Agent Framework

Rust-based AI agent implementing the full plan β†’ act β†’ observe execution loop.

  • Modular tool system with dynamic tool registration and extensibility
  • Async architecture with Tokio for scalable multi-step task execution
  • Memory-safe by design using Rust ownership model
  • Published as a reusable library on crates.io
  • ⭐ 12 stars β€” organic traction from the Rust community

Stack: Rust Β· Tokio Β· LLM APIs Β· Async


πŸ›  Tech Stack

Languages Rust β€’ C++ β€’ Python β€’ Java β€’ Go β€’ TypeScript β€’ Solidity

Systems Pipeline design β€’ Cache modeling β€’ Binary protocols β€’ Memory-mapped I/O β€’ Allocation-free hot paths β€’ NUMA / core pinning β€’ Latency measurement

Backend Tokio β€’ Actix Web β€’ Spring Boot β€’ FastAPI β€’ JAX-RS β€’ Hibernate

Infrastructure Kafka β€’ Redis β€’ Docker β€’ Kubernetes β€’ Terraform β€’ AWS β€’ GitHub Actions

Databases PostgreSQL β€’ MySQL β€’ Amazon S3 β€’ Redshift β€’ Snowflake


🀝 Connect


πŸ’‘ Open to Systems Software / SDE III roles in systems and backend infrastructure.

Pinned Loading

  1. cpu16 cpu16 Public

    A custom 16-bit CPU emulator written from scratch in Rust β€” includes a hand-designed ISA, two-pass assembler, fetch-decode-execute engine, stack, flags register, and interrupt handling.

    Rust 2

  2. tickpipe tickpipe Public

    cpp cpp20 low-latency fpga market-data order-book matching-engine nasdaq itch hft trading-systems systems-programming

    C++ 1