Pin audiodsp at its CircuitPython build fix; a pin change builds the firmware set

.github/workflows/release-firmware.yml

@@ -49,6 +49,8 @@ on:
       - 'scripts/pin_lvgl_ref.sh'
       - 'scripts/stage_firmware_page.py'
       - 'scripts/ci_scope.py'
+      - 'modules.lock'
+      - 'deps.lock'
       - 'test_release_firmware.py'
       - 'test_stage_firmware_page.py'
       - 'test_ci_scope.py'

modules.lock

@@ -19,7 +19,7 @@
 # sibling checkout is linked there instead) and compiles the port for its
 # interpreter. Move the commit here to move every LVGL build, MicroPython's and
 # CircuitPython's.
-audiodsp          https://github.com/PyDevices/audiodsp.git           4873df7a7449b38e39c3575ee3ae75d4fdd92805
+audiodsp          https://github.com/PyDevices/audiodsp.git           c2495f40d7d6556a3a383f9317ecb0bbc42b772c
 omnipython-lvgl   https://github.com/PyDevices/omnipython-lvgl.git    e6f88b7737e3c5252e92a6e717142875127816ca
 pygraphics        https://github.com/PyDevices/pygraphics.git         ecc4eb2348b3289f4383d51c6f401e922621e724
 ulab              https://github.com/v923z/micropython-ulab.git       1d3ddd8f5228e2c7335dac71f4846e6abb0ec9f9

scripts/ci_scope.py

@@ -89,6 +89,8 @@ def cp_reach(path):
 
 FIRMWARE = "scripts/release_firmware.py"
 FIRMWARE_WORKFLOW = ".github/workflows/release-firmware.yml"
+# The pins every build fetches: a change to one can break any board.
+FIRMWARE_PINS = ("modules.lock", "deps.lock")
 
 
 def cells_of(source):
@@ -110,9 +112,10 @@ def firmware_scope(files, show_base, show_head):
 
     The workflow, or anything in release_firmware.py besides CELLS, builds the
     whole set. A change to CELLS builds the cells whose row changed, and the
-    whole set when a cell is added or removed. Everything else the workflow
-    watches is read by the unit tests its gate job runs and by no build."""
-    if FIRMWARE_WORKFLOW in files:
+    whole set when a cell is added or removed. A pin in modules.lock or
+    deps.lock builds the whole set too. Everything else the workflow watches is
+    read by the unit tests its gate job runs and by no build."""
+    if FIRMWARE_WORKFLOW in files or any(p in files for p in FIRMWARE_PINS):
         return True, True, []
     if FIRMWARE not in files:
         return False, False, []

test_ci_scope.py

@@ -69,6 +69,10 @@ def test_the_stager_and_the_tests_build_nothing(self):
     def test_the_workflow_builds_the_whole_set(self):
         self.assertEqual(self.scope([ci_scope.FIRMWARE_WORKFLOW]), (True, True, []))
 
+    def test_a_pin_builds_the_whole_set(self):
+        self.assertEqual(self.scope(["modules.lock"]), (True, True, []))
+        self.assertEqual(self.scope(["deps.lock"]), (True, True, []))
+
     def test_one_cells_row_builds_that_cell(self):
         head = with_cell(SOURCE, "mp-s3-lcd43", 'flash="8MB"', 'flash="16MB"')
         self.assertEqual(self.scope([ci_scope.FIRMWARE], head), (True, False, ["mp-s3-lcd43"]))