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1. adulu-bang/NetStream-Caravel adulu-bang/NetStream-Caravel Public

   NetStream: a lightweight programmable packet-processing SoC with CPU control plane and TCAM-based dataplane (parser -- match -- action), implemented on the Caravel open-source ASIC platform for edg…

   Verilog 2 1

2. Shiken56/Nexus-V Shiken56/Nexus-V Public

   Making a riscv based soc, fpga implementation

   Verilog 1

3. Risc-V_RV32I_pipeline_core Risc-V_RV32I_pipeline_core Public

   A 5 stage RISC-V pipelined processor core in verilog

   Verilog

4. Sobel-edge-detection-fpga Sobel-edge-detection-fpga Public

   Sobel edge detection system implemented on the Nexys 4 DDR FPGA board with real time video processing

   Verilog 1

5. IRIS-Labs-HW-Recs IRIS-Labs-HW-Recs Public

   Forked from Adithya1435/IRIS-Labs-HW-Recs

   Files for IRIS Labs HW Assignment 1

   Verilog

6. RISC-V_single_cycle RISC-V_single_cycle Public

   Work done while pursuing LinuxFoundationX LFD111x Building a RISC-V CPU Core course

   TL-Verilog