feat: drip-scan full-frame single-exposure image capture (SDK) - #168
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boringethan wants to merge 15 commits into
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feat: drip-scan full-frame single-exposure image capture (SDK)#168boringethan wants to merge 15 commits into
boringethan wants to merge 15 commits into
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Companion to camera-fpga#8. Refs #167
Co-Authored-By: Claude Fable 5 <[email protected]>
Co-Authored-By: Claude Fable 5 <[email protected]>
… registers (#167) Co-Authored-By: Claude Fable 5 <[email protected]>
… with overrun) (#167) Co-Authored-By: Claude Fable 5 <[email protected]>
…#167) Co-Authored-By: Claude Fable 5 <[email protected]>
…ly (#167) Co-Authored-By: Claude Fable 5 <[email protected]>
…r-fw histogram framing (#167)
…bleSyncOut, verified timing values (#167) First HIL campaign findings: (1) console-fw validates TriggerFrequencyHz to 1.00-100.00 Hz and boots with EnableSyncOut=false - capture_full_frames now forces SyncOut on and SWEEP_FSIN_HZ=1.0, with HTS retuned 38400->36000 so the 0.987 s frame fits the 1.000 s period; (2) reverted the tc_r/0x3882 'sync point' writes - bench-disproven (0x3881-83 is max_expo_a per datasheet A-18; production runs auto-tc_r). Frame cadence at stretched timing remains open (documented in the profile docstring): trigger_mod streaming mode stops framing when VTS changes; datasheet 3.7 snapshot mode produces correct slow frames but gaps the MIPI clock, resetting the camera FPGA (PLL-loss observed on STATUS bit0) and disarming the sweep after one pushed line. Transport itself is hardware-proven (smoke test: 100+ CRC-clean lines; snapshot: 1 perfect line parsed+assembled end-to-end). Refs #167
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Draft — SDK side of the drip-scan feature (design spec 2026-07-19, camera-fpga#8). Opened as a draft: do not merge until the matched set validates on the rig.
What this adds
TYPE_IMAGEstream byte (0x03),OW_CAMERA_IMAGE_MODE=0x30, pinned sweep/production sensor-timing profiles,OX02C1B_I2C_ADDR.tests/test_pipeline/suite).util_crc16, byte-identical to sensor-fwutils.c, check value 0x29B1), vectorized RAW10 unpacker (pinned bit layout — proven to invert the FPGA packer's own test vector),FrameAssemblerwithframe_cntsingle-exposure enforcement + overrun/wedge tracking,FpgaRegs(FPGA I2C map v2: sweep/overrun/wedge), atomic group-hold sensor retiming, and thecapture_full_framesorchestrator (graduates camera-fpgatools/full_frame_capture/).set_camera_image_mode(enable, mask)(OW_CAMERA_IMAGE_MODE wire format).Tests
33 new software-only unit tests (
tests/test_image_capture.py+tests/test_stream_image_routing.py), all green, with independently-computed golden vectors (line CRC 0xA25E, RAW10 8-px hand vector). Full software suite (drip-scan + pipeline + shim): 271 passed, 30 skipped.Cross-repo / matched set
Depends on the sensor-fw companion (OW_CAMERA_IMAGE_MODE + 2408-B line forwarding) and camera-fpga#8 (register map v2, already sim-complete + Diamond-built). Wire format, CRC, and register semantics were cross-checked against the FPGA RTL and the sensor-fw plan during review. HIL acceptance (bit-exact test-pattern sweep, laser-synced single-exposure frame, histogram-suite regression after a sweep session) runs once all three land on their
nextbranches.Refs #167
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