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feat: Add cbrt intrinsic support for f32 and f64 - #148

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nihalpasham merged 9 commits into
NVIDIA:mainfrom
goog00:feat/cbrt-intrinsic
Jun 12, 2026
Merged

nihalpasham merged 9 commits into
NVIDIA:mainfrom
goog00:feat/cbrt-intrinsic

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@goog00

@goog00 goog00 commented Jun 9, 2026

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Summary

  • Registers cbrtf32 / cbrtf64 placeholder symbols in dialect-mir/src/rust_intrinsics.rs, following the same pattern as existing float math intrinsics
  • Maps them to CUDA libdevice builtins __nv_cbrtf / __nv_cbrt in the MIR-lower call translator
  • Hooks the new placeholders into the codegen collector
  • Adds a cbrt_smoke example: 16 test values × 2 type variants (f32/f64), verifying GPU results are within 2 ULP of host libm

Test plan

  • cargo test -p dialect-mir -p mir-lower --lib — unit tests covering intrinsic name → enum dispatch and arg count
  • cargo oxide run cbrt_smoke — end-to-end GPU smoke test; expected output: SUCCESS: 16 cases × 2 variants within 2 ULP of host libm
  • Verified on RTX 5090 (sm_120a, CUDA 13.0)

@nihalpasham nihalpasham added enhancement New feature or request intrinsics Device intrinsics and libdevice math mappings codegen Device code-generation pipeline (Rust MIR to IR to PTX) labels Jun 10, 2026
…odule]

Main made bare cuda_launch! a caller-unsafe API (NVIDIA#171) after this
example was written, so its host side no longer compiles (E0133). The
typed #[cuda_module] launch path is the safe replacement the other
math examples already use; the 16-value x 2-width host comparison and
the SUCCESS marker are unchanged.
The committed lock pinned the cuda-* path deps at 0.1.0; the workspace
has been at 0.2.1 since the version bump, so any build rewrites the
lock and dirties the tree. Commit the regenerated lock.
CI runs a workspace-wide cargo fmt check; the new test table in
float_math.rs was not rustfmt-clean.
On the pinned toolchain f{32,64}::cbrt inlines down to the
core::num::imp::libm extern declarations, not the std::sys::cmath
shims (those carry atan but only cbrtf128 for cbrt). Reword so the
actually-taken path leads and the cmath spelling is the historical
note.
…him guard

is_intrinsic_lowered_cmath_shim is only consulted inside the
forbidden-std branch of should_collect_from_crate, where every def
path starts with std::, so the core::num::imp::libm arms could never
match. They are also unneeded: core is an allowed crate and those libm
shims are extern "C" declarations with no MIR, so the collector's
existing no-MIR skip already excludes them (verbose build of
cbrt_smoke confirms the 'Skipping extern/intrinsic (no MIR)' path
fires for both). Document the std-only constraint on the guard.
# Conflicts:
#	crates/mir-importer/src/translator/terminator/intrinsics/float_math.rs
@nihalpasham

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Thanks for the nice addition, mirrors the atan lowering #109 . Main moved underneath the PR, so I layered fixups on top:

  • feat(cuda-macros): make cuda_launch\! a caller-unsafe API #171 made bare cuda_launch! caller-unsafe, which broke this example's host build (E0133). Ported it to the #[cuda_module] typed-launch style the other math examples use; kernels, the 16-value x 2-width comparison, and the SUCCESS check are unchanged.
  • Refreshed the stale lockfile (cuda-* 0.1.0 -> 0.2.1).
  • rustfmt on the new importer test table.
  • Module docs now lead with the path the pinned toolchain actually takes: f{32,64}::cbrt reaches device codegen via core::num::imp::libm, not std::sys::cmath.
  • Dropped the core::num::imp::libm::* arms from the collector's cmath shim guard: that guard only runs in the forbidden-std branch, and those shims are extern declarations with no MIR, so the collector's no-MIR skip already excludes them. Your importer-side core arms are the load-bearing ones and stay.

cbrt_smoke.ll declares and calls __nv_cbrtf / __nv_cbrt on sm_90.

Completes the coordination between the libm interception table (NVIDIA#142)
and the cbrt lowering (NVIDIA#148): the libm-crate spellings now reach the
same libdevice __nv_cbrt{,f} path as the core ones.
@nihalpasham
nihalpasham merged commit cd8303a into NVIDIA:main Jun 12, 2026
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codegen Device code-generation pipeline (Rust MIR to IR to PTX) enhancement New feature or request intrinsics Device intrinsics and libdevice math mappings

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